Water is an important parameter for crop growth, and the information about the moisture content in soil at different depths is very useful for farmers to determine the best time to water the soil and to irrigate farmland so as to maximize their yield. This thesis project aims to develop a prototype of a multi-depth moisture sensor probe that is part of a large sensing system used in agriculture. The sensor probe has three sets and is required to last for 6-12 months of usage and to be reproduced at a low cost. The sensor probe consists of three sensor boards, on each of which has two different capacitive based sensors and one analog temperature sensor. The three boards are placed approximately 20 cm from each other in the probe. During this project, the two capacitive based sensors were developed, one with arc-shaped plates operating at a frequency less than 1 MHz, and one with electrodes in the form of annular rings operating at a high frequency, approximately 100 MHz. The moisture content in the soil is calculated based on the measurement of the frequency, which depends on the dielectric constant of the soil. For the implementation of the sensor probe, three printed circuit boards (PCBs) for the sensor boards were designed using Altium Designer and then ordered; an STM32 Nucleo board with low power microcontroller was used and the software was implemented in STM32CubeIDE. The lifetime of the sensor probe was calculated for different duty-cycles. With a duty-cycle of 15 minutes, where the sensor probe is active for 1 minute and in sleep mode for 14 minutes, the lifetime of the sensor probe would only be 16 days. With a duty-cycle of 120 minutes instead, with the sensor probe being active for 1 minute, the lifetime is increased to 130 days (less than4,5 months). Due to challenges with the high frequency capacitive sensor, the multi-depth sensor probe does not fully work, and thus cannot be tested with a large testbed. Further work needs to be conducted on the high frequency capacitive sensor and the communication with the gateway.

New and more capable electronics are required to push forward future space missions, and to pursue this goal the first step is the evaluation of novel technologies. The present thesis tackles the problem of evaluating new FPGA and memory technologies for spaceborne missions, while assessing its benefits and improvements. In this project, a novel soft SoC design based on the existing MDPA device was proposed and implemented. The new design includes a memory controller for the DDR3 technology, while targets a new radiation hardened FPGA technology. Additionally, the rad-hard FPGA is also assessed with the Cortex-R5 CPU to push its capabilities up to the limits. This latter, to find out how feasible is to use this FPGA to implement modern soft microprocessors. The thesis demonstrates that the new FPGA technology is able to match the current timing and resources requirements of the MDPA while improving its reliability. Also, it proves that the DDR3 technology has benefits over internal RAM in terms of bandwidth and capacity. Finally, it shows some problems when trying to use the FPGA technology to implement the Cortex-R5 CPU. / Ny och bättre elektronik behövs för att främja framtida rymduppdrag, och för att uppnå detta mål är ett första steg att utvärdera ny teknik. Denna avhandling behandlar problemet att utvärdera nya FPGAoch minnestekniker för uppdrag i rymden, och samtidigt avgöra vilka fördelar som finns med teknikerna och föreslå förbättringar. I detta projekt föreslogs och implementerades en ny mjuk SoCdesign baserad på den befintliga MDPA-enheten. Den nya designen inkluderar en minneskontroll för DDR3-tekniken, och är ämnad att byggas med hjälp av ny strålningshärdad FPGA-teknik. Dessutom testades den strålningshärdade FPGA-tekniken med Cortex-R5-CPU:n för att driva teknikens kapacitet till sin gräns. Detta för att avgöra om det är rimligt att använda denna FPGA för att implementera moderna mjuka mikroprocessorer. Avhandlingen visar att den nya FPGA-tekniken kan matcha de rådande tidsoch resurskraven på MDPA samtidigt som den förbättrar tillförlitligheten. Avhandlingen visar också att DDR3-tekniken har fördelar jämfört med intern RAM vad gäller bandbredd och kapacitet. Avhandlingen beskriver också några problem som uppstår när man försöker använda FPGA-tekniken för att implementera Cortex-R5-CPU:n.

Disc golf is one of the fastest growing sports in Sweden and the countrywide playerbase is steadily growing. In order to meet this increased demand, municipalities and sports associations alike have built new courses all around the country, which all require maintenence. Without an accurate way of determining course usage, it's difficult to guage how much money should be put towards maintaining and developing additional courses. The aim of this project was to design and test a people-counting system for disc golf couses which could provide this information to both players and course owners. Computer vision, wireless communication and sensor technologies were core topics explored during the development of the working prototype.

Multi-Processor System on Chip (MPSoC) consisting of multiple processing cores connected via a Network on Chip (NoC) has gained prominence over the last decade. Most common way of mapping applications to MPSoCs is by dividing the application into small tasks and representing them in the form of a task graph where the edges connecting the tasks represent the inter task communication. Task scheduling involves mapping task to processor cores so as to meet a specified deadline for the application/task graph. With increase in system complexity and application parallelism, task communication times are tending towards task execution times. Hence the NoC which forms the communication backbone for the cores plays a critical role in meeting the deadlines. In this thesis we present an approach to synthesize a minimal network connecting a set of cores in a MPSoC in the presence of deadlines. Given a task graph and a corresponding task to processor schedule, we have developed a partitioning methodology to generate an efficient interconnection network for the cores. We adopt a 2-phase design flow where we synthesize the network in first phase and in second phase we perform statistical analysis of the network thus generated. We compare our model with a simulated annealing based scheme, a static graph based greedy scheme and the standard mesh topology. The proposed solution offers significant area and performance benefits over the alternate solutions compared in this work.

Autonomous vehicles rely on real-time embedded systems called Electronic Control Units (ECUs) and it is crucial for safety and behavioural correctness that ECUs run fast enough, in other words, within their deadlines. In this thesis a high-performance ECU used at Volvo Autonomous Solutions (V.A.S.) running PetaLinux will be evaluated. To ensure that the ECU is able to run in real-time, it will be evaluated by simulating physical models in the form of Functional Mock-up Units (FMUs) that are cross compiled to aarch64. The ECU execution time will be measured to evaluate whether the models run in real-time and to compare it with the performance of a desktop computer. With the use of profiling tools, possible bottlenecks in the utilization of ECU will be identified. The results show that the ECU is capable of running the FMU simulation models faster than real-time and that the ECU runs at less than 10% of the speed of the desktop computer. FMU communication frequency, underutilization of available instructions, unnecessary allocation and unnecessary use of synchronization primitives where identified as the key possible bottlenecks. We conclude that the ECU is likely capable of running significantly more computationally demanding models in real-time if they are optimized for the ECU.

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Introduction: Software reuse by copying and modifying components to fit new systems is common in industrial settings. However, it can lead to multiple variants that complicate testing and maintenance. Therefore, it is beneficial to detect the variants in existing codebases to document or incorporate them into a systematic reuse process. For this purpose, model-based clone detection and variability management can be used. Unfortunately, current tools have too high computational complexity to process multiple Simulink models while finding commonalities and differences between them. Therefore, we explore a novel approach called MatAdd that aims to enable large-scale industrial codebases to be processed. Objective: The primary objective is to process large-scale industrial Simulink codebases to detect the commonalities and differences between the models. Context and method: The work was conducted in collaboration with Addiva and Alstom to detect variants in Alstom's codebase of Simulink models. Alstom has specific modeling guidelines and conventions that the developers follow. Therefore, we used an exploratory case study to change the research direction depending on Alstom's considerations. Results and Conclusions: The results show that MatAdd can process large-scale industrial Simulink codebases and detect the commonalities and differences between its models. MatAdd processed Alstom's codebase that contained 157 Simulink models with 7820 blocks and 9627 lines in approximately 90 seconds and returned some type-1, type-2, and type-3 clones. However, current limitations cause some signals to be missed, and a more thorough evaluation is needed to assess its future potential. MatAdd's current state assists developers in finding clones to manually encapsulate into reusable library components or find variants to document to facilitate maintenance.

Current FPGA technology has advanced to the point that useful embedded System-on-Programmable-Chips (SoPC)s can now be designed. The Real Time Processor (RTP) project leverages the advances in FPGA technology with a system architecture that is customizable to specific real-time applications. The design and implementation of the framework for architecting such a system from ANSI-C code is presented. The Small Device C Compiler (SDCC) was retargeted to the RTP architecture and extended to produce a generator directive file. The RTPGen hardware generator was created to consume the directive file and produce a highly customized top-level structural VHDL file that can be synthesized and programmed onto an FPGA such as the Xilinx Spartan-3. Thus, an application specific multiprocessor real-time embedded system is realized from ANSI-C code.

Verification and validation of embedded systems software is tedious and time consuming. Software model checking uses a tool-based approach automating this process. In order to more accurately model software it is necessary to provide hardware support that enables the execution of software as it should run on native hardware. Hardware support often requires the creation of model checking tools specific to the instruction set architecture. The creation of software model checking tools is non-trivial. We present a strategy for using an "off-the-shelf" model checking tool, Bogor, to provide support for multiple instruction set architectures. Our strategy supports key hardware features such as instruction execution, exceptional control flow, and interrupt servicing as extensions to Bogor. These extensions work within the tool framework using existing interfaces and require significantly less code than creating an entire model checking tool.