The high-voltage SiC power semiconductor devices have been developed in recent years. They cause an urgent in the need for the power semiconductor packaging to have not only low interconnect resistance, less noise, less parasitic oscillations, improved reliability, and better thermal management, but also High-Voltage (HV) blocking capability. The existing power semiconductor packaging technologies includes wire-bonding interconnect, press pack, flip-chip technology, metal posts interconnected parallel plates structure (MIPPS), dimple array interconnection (DAI), power overlay (POL) technology, and embedded power (EP) technology. None of them meets the requirements of low profile and high voltage rating. The objective of the work in this dissertation is to propose and design a high-voltage power semiconductor device packaging method with low electric field stress and low profile to meet the requirments of high-voltage blocking capability. The main contributions of the work presented in this dissertation are: 1. Understanding the electric field distribution in the package. The power semiconductor packaging is simulated by using Finite Element Analysis (FEA) software. The electric field distribution is known and the locations of high electric field concentration are identified. 2. Development of planar high-voltage power semiconductor device packaging method With the proposed structure in the dissertation, the electric field distribution of a planar device package is improved and the high electric field intensity is relieved. 3. Development of design guidelines for the propsed planar high-voltage device packaging method. The influence of the structure dimensions and the material properties is studied. An optimal design is identified. The design guideline is given. 4. Fabrication and experimental verification of the proposed high-voltage device packaging method A detailed fabrication procedure which follows the design guideline is presented. The fabricated modules are tested by using a high power curve tracer. Test results verify the proposed method. 5. Simplification of the structure model of the proposed device package The package structure model is simplified through the elimination of power semiconductor device internal structure model. The simplified model can be simulated by a non-power device simulator. The simulation results of the simplified model match the simulation results of the complete model very well. / Ph. D.

Because of the shortage of domestic energy resources in Taiwan, more than 97% of the energy has to be imported. The energy price has been increased dramatically during recent years due to the limited supply of conventional primary fossil energy resources. With the economic development and upgrade of people living standard, the electricity power consumption is increased significantly. To solve the problem, different strategies of energy conservation and CO2 emission reduction have been promoted by government to reduce that the peak loading growth and achieve better usage of electricity with more effective load management. This thesis proposes a digital smart meter which integrates the energy metering IC, microprocessor and hybrid communication schemes (Power Line Carrier/ZigBee/RS-485). The load control module and communication module are included in the smart meter to support various application functions. The embedded power management system (PMS) is also proposed to integrate with the smart meter to perform the demand response according to the real-time pricing and load management for residential and commercial customers. The master station can supervise the real-time power consumption of various load components to analyze the power consumption model of customers served and execute the demand load control. The actual demonstration system of embedded PMS has been set up to verify the function of energy management so that the customers have better understanding of power consumption by each appliance. In the future, the implementation of intelligent load control with an emergency load shedding of capability can help utility companies to achieve virtual power generation to enhance the power systems reliability. The customers may also reduce the electricity charge by executing demand response function, which disconnects the electricity service for non essential loads for either system emergency or high electricity peak pricing

abstract: The holomorphic embedding method (HEM) applied to the power-flow problem (HEPF) has been used in the past to obtain the voltages and flows for power systems. The incentives for using this method over the traditional Newton-Raphson based nu-merical methods lie in the claim that the method is theoretically guaranteed to converge to the operable solution, if one exists. In this report, HEPF will be used for two power system analysis purposes: a. Estimating the saddle-node bifurcation point (SNBP) of a system b. Developing reduced-order network equivalents for distribution systems. Typically, the continuation power flow (CPF) is used to estimate the SNBP of a system, which involves solving multiple power-flow problems. One of the advantages of HEPF is that the solution is obtained as an analytical expression of the embedding parameter, and using this property, three of the proposed HEPF-based methods can es-timate the SNBP of a given power system without solving multiple power-flow prob-lems (if generator VAr limits are ignored). If VAr limits are considered, the mathemat-ical representation of the power-flow problem changes and thus an iterative process would have to be performed in order to estimate the SNBP of the system. This would typically still require fewer power-flow problems to be solved than CPF in order to estimate the SNBP. Another proposed application is to develop reduced order network equivalents for radial distribution networks that retain the nonlinearities of the eliminated portion of the network and hence remain more accurate than traditional Ward-type reductions (which linearize about the given operating point) when the operating condition changes. Different ways of accelerating the convergence of the power series obtained as a part of HEPF, are explored and it is shown that the eta method is the most efficient of all methods tested. The local-measurement-based methods of estimating the SNBP are studied. Non-linear Thévenin-like networks as well as multi-bus networks are built using model data to estimate the SNBP and it is shown that the structure of these networks can be made arbitrary by appropriately modifying the nonlinear current injections, which can sim-plify the process of building such networks from measurements. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

With the development of information technology, power management for telecom and computer applications become a large market for power supply industries. To meet the performance and reliability requirement, distributed power system (DPS) is widely adopted for telecom and computer systems, because of its modularity, maintainability and high reliability. Due to limited space and increasing power consumption, power supplies for telecom and server systems are required to deliver more power with smaller volume. As the key component of DPS system, front-end AC/DC converter is under the pressure of continuously increasing power density. For conventional industry practices, some limitations prevents front-end converter meeting the power density requirement. In this dissertation, different techniques have been investigated to improve power density of front-end AC/DC converters. For PFC stage, at low switching frequency, PFC inductor size is large and limits the power density. Although increasing switching frequency can dramatically reduce PFC inductor size, EMI filter size might be larger at higher switching frequency because of the change of noise spectrum. Since the relationship between EMI filter size and PFC switching frequency is unclear for industry, PFC circuits always operate with switching frequency lower than 150 kHz. Based on the EMI filter design method, together with a simple EMI noise prediction model, relationship between EMI filter corner frequency and PFC switching frequency was revealed. The analysis shows that switching frequency of PFC circuit should be higher than 400 kHz, so that both PFC inductor and EMI filter size can be reduced. Although theoretical analysis and experimental results verify the benefits of high switching frequency PFC, it is essential to find a suitable topology that allows high switching frequency operation while maintains high efficiency. Three PFC topologies, single switch PFC, three-level PFC with range switch and dual Boost PFC, were evaluated with analysis and experiments. By using advanced semiconductor devices, together with proposed control methods, these topologies could achieve high efficiency at high switching frequency. Thus, the benefits of high frequency PFC can be realized. In front-end converter, large holdup time capacitor size is another barrier for power density improvement. To meet the holdup time requirement, bulky holdup time capacitor is normally used to provide energy during holdup time. Holdup time capacitor requirement can be reduced by using wider input voltage range DC/DC converte. Because LLC resonant converter can realized with input voltage range without sacrificing its normal operation efficiency, it becomes an attractive solution for DC/DC stage of front-end converters. Moreover, its small switching loss allows it operating at MHz switching frequency and achieves smaller passive component size. However, lack of design methodology makes the topology difficult to be implemented. An optimal design methodology for LLC resonant converter has been developed based on the analysis on the circuit during normal operation condition and holdup time. The design method is verified by a 1 MHz switching frequency LLC resonant converter with 76W/in3 power density. When front-end converter operates at high switching frequency, negative effects of circuit parasitics become more pronounced. By integrating active devices together with their gate drivers, Active Integrated power electronics module (IPEM) can largely reduce circuit parasitics. Therefore, switching loss and voltage stress on switching devices can be reduced. Moreover, IPEM concept can be extended into passive integration and EMI filter integration By using this power integration technology, power density and circuit performance of front-end converter can be improved, which is verified by theoretical analysis and experimental results. / Ph. D.