Almost all electronic devices require efficient conversion of electrical power from one form to another. Electrical power is used world wide at the rate of approximately 12 billion kW per hour. The Center for Power Electronics Systems at Virginia Tech was established with a vision to develop an integrated systems approach via integrated power electronic modules (IPEMs) to improve the reliability, cost-effectiveness, and performance of power electronics systems. IPEMs are multi-layered structures based on embedded power technology and offer the advantage of three-dimensional (3D) packaging of electronic components in a small and compact volume, replacing the traditional wire bonding technology. They have the potential to offer reduced time and effort associated with developing and manufacturing power processors. However, placing multiple heat generating chips in a small volume also makes thermal management more challenging. With the steady increase in the heat density of the electronic packages during the last few decades, thermal management is becoming a key enabling technology for the future growth of power electronics. The focus of this work is on using computational analysis tools and experimental techniques to assess fundamental and practical cooling limitations on IPEMs, developing both passive and active integrated thermal management strategies, and creating design guidelines for IPEMs based on both thermal and thermo-mechanical stress considerations. Specifically, a commercially available finite element package is used to create a 3D geometric layout of the electronic module. The baseline finite element numerical model is validated using bench-top wind tunnel experiments. The experimental setup is also employed to characterize the thermal behavior of chips in the multi-chip package and test the applicability of superposition methodology for temperature fields of chips within multi-chip modules. Using numerical models, both passive and active integrated thermal management strategies are investigated. The passive cooling strategies include advanced ceramic materials, copper trace thickness, and structural enhancements. Active cooling strategies include double-sided cooling using traditional heat sinks, and an extension of double-sided cooling concept using microchannels integrated with the module on both sides of embedded chips. The overall result of the work presented here is the better understanding of thermal issues and limitations with IPEM technology, and development of thermal design guidelines for cooling strategies that take into consideration both thermal and thermo-mechanical performance. / Ph. D.

In modern power electronics systems there is a growing trend to replace discrete devices with integrated power electronic modules (IPEMs). In this way, several components can be replaced by a single component. By using prefabricated building blocks, the engineer simplifies the design process, reducing the total design cycle time and cost. By integrating only the necessary components to provide power switching, the end user has a pre-optimized building block with the flexibility to be used in a large variety of applications. Besides simplifying the design process, power modules should be designed in such a way as to improve the performance of the power converter. This begs the question as to how best to judge if one IPEM has better performance than another or better performance than its discrete counterpart. In analyzing a converter's performance, popular criteria include efficiency, power density, device stresses, and EMI. All of these criteria are strongly linked to the switching characteristics of the IPEM's power devices. This thesis is a comprehensive study of the requirements for obtaining and analyzing the switching characteristics of the IPEM's power devices. It outlines the important switching characteristics and the implications of each characteristic on converter performance. It deals with the relevant measurement issues, specifically addressing the minimum requirements, which sensors are most suitable, and problems leading to inaccurate data. A parametric study is conducted to determine the effects of several circuit and operating parameters on the switching characteristics. Using the resulting data and the knowledge from the measurement study, we can decide how to design the testbed layout, what operating conditions should be chosen for testing, and what effects of the tester must be decoupled to truly see the effects of IPEM design. The thesis concludes with the design of standard test equipment and procedures. / Master of Science

The software environment for power electronics design is comprised of tools that address many interrelated disciplines including circuits design, physical layout, thermal management, structural mechanics, and electromagnetics. This usually results in a number of separate models that provide various views of a design, each of which is usually stored separately in proprietary formats. The problem is that the relationships between views (e.g., the circuit design that defines the functional connectivity between components, and the physical layout that provides physical paths to implement connections), are not explicitly captured. This makes it difficult to synchronize and maintain data consistency across all models as changes are made to the respective views. This thesis addresses this problem by describing power electronics modules using STEP AP210, the STandard for the Exchange of Product data, Application Protocol 210; which has been designated as ISO 10303-210. A multidisciplinary model was implemented for an integrated power electronics module (IPEM). It consists of two views of the IPEM: a functional network definition of the IPEM, and a physical implementation that satisfies the functional connectivity requirements. The relationships between these two views are explicitly recorded in the model. These relationships allow for the development of a method which verifies whether the connectivity data in both views are consistent. Finally, this thesis provides guidance for deploying STEP AP210 to unify multidisciplinary data resources during the design of integrated power electronics. / Master of Science

Exploring RF models for an integrated power electronics module (IPEM) is crucial to analyzing and predicting its EMI performance. This thesis deals with the parasitics extraction approach for an active IPEM in a frequency range of 1MHz through 30MHz. Based on the classic electromagnetic field theory, the calculating equations of DC and AC parameters for a 3D conducting structure are derived. The influence of skin effect and proximity effect on AC resistances and inductances is also investigated at high frequencies. To investigate RF models and EMI performance of the IPEM, a 1kW 1MHz series resonant DC-DC converter (SRC) is designed and fabricated in this work. For extracting the stray parameters of the built IPEM, two main software simulation tools ¡ª Maxwell Quick 3D Parameter Extractor (Maxwell Q3D) and Maxwell 3D Field Simulator (Maxwell 3D), prevailing electromagnetic simulation products from Ansoft Corporation, are introduced in this study. By trading off between the numerical accuracy and computational economy (CPU time and consumption of memory size), Maxwell Q3D is chosen in this work to extract the parameters for the full bridge IPEM structure. The step-by-step procedure of using Maxwell Q3D is presented from pre-processing the 3D IPEM structure to post-processing the solutions, and exporting equivalent circuit for PSpice simulations as well. RF modeling of power MOSFETs is briefly introduced. In order to verify extracted parameters, in-circuit impedance measurements for the IPEM using Agilent 4294A Impedance Analyzer together with Agilent 42941A probe are then followed. Measured results basically verify the extracted data, while the discrepancy between measured results and simulated results is also analyzed. / Master of Science

This dissertation presents a systematic design and demonstration of a novel solid-state DC circuit breaker. The mechanical circuit breaker is widely used in power systems to protect industrial equipment during fault or abnormal conditions. Compared with the slow and high-maintenance mechanical circuit breaker, the solid-state circuit breaker is capable of high-speed interruption of high currents without generating an arc, hence it is maintenance-free. Both the switch and the tripping unit are solid-state, which meet the requirements of precise protection and high reliability. The major challenge in developing and adopting a solid-state circuit breaker has been the lack of power semiconductor switches that have adequate current-carrying capability and interruption capability. The high-speed, high-current solid-state DC circuit breaker proposed and demonstrated here uses a newly-emerging power semiconductor switch, the emitter turn-off (ETO) thyristor as the main interruption switch. In order to meet the requirement of being a high-current circuit breaker, ETO parallel operation is needed. Therefore the major effort of this dissertation is dedicated to the development of a high-current (5000A) DC switch module that utilizes multiple ETOs in parallel. This work can also be used to develop an AC switch module by changing the asymmetrical ETOs used to symmetrical ETOs. An accurate device model of the ETO is needed for the development of the high-current DC switch module. In this dissertation a novel physics-base lumped charge model is developed for the ETO thyristor for the first time. This model is verified experimentally and used for the research and development of the emitter turn-off (ETO) thyristor as well as the DC switch module discussed in this dissertation. With the aid of the developed device model, the device current sharing between paralleled multiple ETO thyristors is investigated. Current sharing is difficult to achieve for a thyristor-type device due to the large device parameter variations and strong positive feedback mechanism in a latched thyristor. The author proposes the "DirectETO" concept that directly benefits from the high-speed capability of the ETO and strong thermal couplings among ETOs. A high-current DC switch module based on the DirectETO can be realized by directly connecting ETOs in parallel without the bulky current sharing inductors used in other current-sharing solutions. In order to achieve voltage stress suppression under high current conditions, the parasitic parameters, especially parasitic inductance in a high-current ETO switch module are studied. The Partial Element Equivalent Circuit (PEEC) method is used to extract the parasitics. Combined with the developed device model, the electrical interactions among multiple ETOs are investigated which results in structural modification for the solid-state DC switch module. The electro-thermal model of the DC switch module and the heatsink subsystem is used to identify the "thermal runaway" phenomenon in the module that is caused by the negative temperature coefficient of the ETO's conduction drop. The comparative study of the electro-thermal coupling identifies a strongly-coupled thermal network that increases the stability of the thermal subsystem. The electro-thermal model is also used to calculate the DC and transient thermal limit of the DC switch module. The high-current (5000A) DC switch module coupled with a solid state tripping unit is successfully applied as a high-speed, high-current solid-state DC circuit breaker. The experimental demonstration of a 5000A current interruption shows an interruption time of about 5 microseconds. This high-speed, high-current DC switch module can therefore be used in DC circuit breaker applications as well as other types of application, such as AC circuit breakers, transfer switches and fault current limiters. Since the novel solid-state DC circuit breaker is able to extinguish the fault current even before it reaches an uncontrollable level, this feature provides a fast-acting, current-limiting protection scheme for power systems that is not possible with traditional circuit breakers. The potential impact on the power system is also discussed in this dissertation. / Ph. D.

With the development of information technology, power management for telecom and computer applications become a large market for power supply industries. To meet the performance and reliability requirement, distributed power system (DPS) is widely adopted for telecom and computer systems, because of its modularity, maintainability and high reliability. Due to limited space and increasing power consumption, power supplies for telecom and server systems are required to deliver more power with smaller volume. As the key component of DPS system, front-end AC/DC converter is under the pressure of continuously increasing power density. For conventional industry practices, some limitations prevents front-end converter meeting the power density requirement. In this dissertation, different techniques have been investigated to improve power density of front-end AC/DC converters. For PFC stage, at low switching frequency, PFC inductor size is large and limits the power density. Although increasing switching frequency can dramatically reduce PFC inductor size, EMI filter size might be larger at higher switching frequency because of the change of noise spectrum. Since the relationship between EMI filter size and PFC switching frequency is unclear for industry, PFC circuits always operate with switching frequency lower than 150 kHz. Based on the EMI filter design method, together with a simple EMI noise prediction model, relationship between EMI filter corner frequency and PFC switching frequency was revealed. The analysis shows that switching frequency of PFC circuit should be higher than 400 kHz, so that both PFC inductor and EMI filter size can be reduced. Although theoretical analysis and experimental results verify the benefits of high switching frequency PFC, it is essential to find a suitable topology that allows high switching frequency operation while maintains high efficiency. Three PFC topologies, single switch PFC, three-level PFC with range switch and dual Boost PFC, were evaluated with analysis and experiments. By using advanced semiconductor devices, together with proposed control methods, these topologies could achieve high efficiency at high switching frequency. Thus, the benefits of high frequency PFC can be realized. In front-end converter, large holdup time capacitor size is another barrier for power density improvement. To meet the holdup time requirement, bulky holdup time capacitor is normally used to provide energy during holdup time. Holdup time capacitor requirement can be reduced by using wider input voltage range DC/DC converte. Because LLC resonant converter can realized with input voltage range without sacrificing its normal operation efficiency, it becomes an attractive solution for DC/DC stage of front-end converters. Moreover, its small switching loss allows it operating at MHz switching frequency and achieves smaller passive component size. However, lack of design methodology makes the topology difficult to be implemented. An optimal design methodology for LLC resonant converter has been developed based on the analysis on the circuit during normal operation condition and holdup time. The design method is verified by a 1 MHz switching frequency LLC resonant converter with 76W/in3 power density. When front-end converter operates at high switching frequency, negative effects of circuit parasitics become more pronounced. By integrating active devices together with their gate drivers, Active Integrated power electronics module (IPEM) can largely reduce circuit parasitics. Therefore, switching loss and voltage stress on switching devices can be reduced. Moreover, IPEM concept can be extended into passive integration and EMI filter integration By using this power integration technology, power density and circuit performance of front-end converter can be improved, which is verified by theoretical analysis and experimental results. / Ph. D.