A convolutional neural network (CNN) is a deep learning framework that is widely used in computer vision. A CNN extracts important features of input images by perform- ing convolution and reduces the parameters in the network by applying pooling operation. CNNs are usually implemented with programming languages and run on central process- ing units (CPUs) and graphics processing units (GPUs). However in recent years, research has been conducted to implement CNNs on field-programmable gate array (FPGA). The objective of this thesis is to implement a CNN on an FPGA with few hardware resources and low power consumption. The CNN we implement is for digits recognition. The input of this CNN is an image of a single digit. The CNN makes inference on what number it is on that image. The performance and power consumption of the FPGA is compared with that of a CPU and a GPU. The results show that our FPGA implementation has better performance than the CPU and the GPU, with respect to runtime, power consumption, and power efficiency.

How can Linux reduce the time required for development in embedded systems, and what makes Linux appealing to embedded developers despite the loss in overall control? Through qualitative interviews with industry professionals and a systematic literature review, challenges and benefits of using Linux in embedded systems development were identified and discussed. Three hypotheses were formulated based on recurring topic agreement among the interview subjects: Reduced development time through the use of open-source solutions, struggles with real-time and security requirements, and challenges within troubleshooting and dependency management. The empirical data observed primarily aligned with the professional perception indicating the potential for development time reduction leveraging resources properly. However also highlighting additional challenges that are not present in traditional embedded system development. Several trade-offs were observed from the findings, including increased overhead and licensing concerns. Further research is required to fully understand the advantages, challenges and limits associated with Linux in an embedded system environment. This study provides valuable insights for future exploration within the field.

The introduction of smart grid technology has changed the way traditional power grid network function. It made the grid structure more dynamic by enhancing electrical usage management capability. Also, it has increased the scope to enhance communication infrastructure in a smart grid structure. The current smart grid solution is based on IEC 61850 architecture where the exchange of information between the electrical utilities is over the fast Ethernet LAN connection. This communication mechanism is fast, efficient but lacks scalability, flexibility and less susceptible to failure. Also, earlier technical paper from IEC 61850 standard was for communication within a substation. Wide Area Monitoring Protection and Control implementation which utilizes coherent real time synchrophasor information would play a vital role in realizing the utility physical status. IEC 61850-90-5, a new technical report from International Electrotechnical Commission provides the mechanism to transmit and receive the synchrophasor information using the advance IP protocol over a wireless communication infrastructure for WAMPAC application. IEC 61850-90-5 provide a way to exchange routable synchrophasor information over public IP network such as LTE, WiMax, WLAN, etc. Out of all the available wireless solution, LTE provides high flexibility, distance coverage, data rate with low latency and hence can play an important role in replacing the existing communication structure in a smart grid. The thesis work evaluates the performance and applicability of LTE for smart grid communication. An IEC 61850-90-5 communication model utilizing UDP/IP protocol to transmit and receive data over the LTE network was developed from the open source project. The modified model was used to benchmark the performance of LTE. Different communication metrics such as reliability, availability, latency, and throughput was evaluated to benchmark the performance of LTE for time critical smart grid application. The metrics were measured for different packet sizes and transmission rates combination. The result shares some interesting findings on the readiness of LTE for smart grid solution. It is concluded that cellular network can play an important role in realizing communication infrastructure in a smart grid application.

Controller Area Network (CAN) is a communication bus designed in the 90s to make simple androbust in-vehicle networks. However, as vehicles are becoming more complex, higher performanceCAN protocols were introduced to manage the expanding volumes of real-time data and more strictsafety requirements. This resulted in the development of next-generation CAN protocols, i.e. CANwith Flexible Data rate (CAN FD) and CAN Extra Long (CAN XL). Response-Time Analysis(RTA) of CAN was developed as a tool to verify if all messages on the CAN bus meet their timingrequirements, i.e. meet their deadlines. Existing RTA is revisited and its applicability on CAN XLmessages is analyzed in the thesis. RTA with priority-based queueing policy, but also RTA whichconsiders different buffer limitations is also revisited. This thesis developed an analytical modelfor Worst-Case Transmission Time (WCTT) calculations for CAN XL which is a prerequisite forits RTA. Finally, MPS-CAN Analyzer and industrial tool suit Rubus-ICE are extended to supportRTA of both CAN FD and CAN XL. The extended tools were used to implement two use casesconsisting of the number of CAN, CAN FD and CAN XL messages. Several experiments wereconducted to compare the performance of different CAN generations in terms of response times ofthe messages. The results indicate that larger data payloads should be sent using next-generationCAN protocol with their bit-rate switching option enabled. Nodes implementing abortable and nonabortablebuffers were also analyzed in the two experiments. Small differences in the response timesof the messages were noticed when buffer limitations are considered.

Energy systems need to evolve to meet the requirements of the modern world and the future. Hence, substantial effort is needed at an academic and industrial level to develop valuable diagnostic techniques. One current limitation of developing these diagnostic techniques is a lack of data on significant changes in the power signal (voltage and current). Producing sufficient data would require the deployment of data acquisition units that can record events of interest. These data acquisition units could be embedded systems deployed in the field. One way to detect changes in the signal is via a waveform prediction algorithm. Hence, waveform prediction will play a significant role in developing the trigger mechanism for monitoring algorithms as predicting a waveform a few cycles ahead allow the triggering of desired events. This thesis aims to find suitable machine-learning models for online and real-time time series prediction that predict the nominal state of a power signal waveform and could be used to detect significant events to activate a trigger mechanism in data acquisition devices. In this thesis, three different machine-learning models: Accurate Online Support Vector Regression (AOSVR), online Autoregressive Integrated Moving Average (ARIMA), and online Gated Recurrent Units (GRU) are implemented on a Raspberry Pi 3B+ and compared to each other in the aspects of computation time and error. Rigorous testing results demonstrate that the AOSVR had the lowest average operation in all the tested sampling rates, while the ARIMA had the overall lowest prediction time and lowest error when tested on data with sampling rates up to 2.5 kHz. Furthermore, all the models were able to produce a trigger at significant events. The results of this thesis could be used by the industry to further the development of diagnostic techniques, as well as increase the general knowledge of machine-learning applications on embedded systems.

In this work, two MPPT algorithms have been implemented and evaluated in an existing solar charger from the company Solar Bora. This with the aim of evaluating which algorithm performs best in terms of power production and stability in the system in question. Another goal in this work was to develop the solar cell charger with support for several input channels to be able to connect several solar cell panels. This with the aim of giving more redundancy to the system and further increasing power production. The challenge that arose regarding multiple channels was about how the channels would be balanced among themselves in a stable way. As a minor part of this work, it was also included to evaluate whether a minor hardware optimization was possible. The purpose of this was also to increase power production. The result of this work regarding how the MPPT algorithms perform is in line with the theory presented in the theory part. / I detta arbete har två MPPT-algoritmer implementerats och utvärderats i en befintlig solcellsladdare från företaget Solar Bora. Detta med syfte att utvärdera vilken algoritm som presterar bäst i form av effektproduktion och stabilitet i systemet i fråga. Ytterligare ett mål i detta arbete var att utveckla solcellsladdaren med stöd för flera in-kanaler för att kunna ansluta flera solcellspaneler. Detta med syfte att ge mera redundans till systemet samt öka effektproduktionen ytterligare. Utmaningen som uppstod gällande multipla kanaler handlade om hur kanalerna skulle balanseras sinsemellan på ett stabilt sätt. Som en mindre deluppgift i detta arbete ingick även att utvärdera huruvida en mindre hårdvaruoptimering var möjlig. Syftet med denna var också att öka effektproduktionen. Resultatet i detta arbete gällande hur MPPT-algoritmerna presterar stämmer överens med den teori som presenteras i teoridelen.

Profiling of an application identifies parts of the code being executed using the hardware performance counters thus providing the application’s performance. Profiling has long been standard in the development process focused on a single execution of a single program. As computing systems have evolved, understanding the bigger picture across multiple machines has become increasingly important. As supercomputing grows in pervasiveness and scale, understanding parallel applications performance and utilization characteristics is critically important, because even minor performance improvements translate into large cost savings. The study surveys various tools for the application. After which, Perfminer was integrated in SCANIA’s Linux clusters to profile CFD and FEA applications exploiting the batch queue system features for continuous system wide profiling, which provides performance insights for high performance applications, with negligible overhead. Perfminer provides stable, accurate profiles and a cluster-scale tool for performance analysis. Perfminer effectively highlights the micro-architectural bottlenecks. / Profilering av en ansökan identifierar delar av koden exekveras med hjälp av hårdvara prestandaräknare därmed ger programmets prestanda. Profilering har länge varit standard i utvecklingsprocessen fokuserad på en enda exekvering av ett enda program. Som datorsystem har utvecklats, att förstå helheten på flera datorer har blivit allt viktigare. Som superdatorer växer i genomslagskraft och skala, är förståelsen parallella applikationer prestanda och användningsegenskaper avgörande betydelse, eftersom även prestandaförbättringar mindre översätta till stora kostnadsbesparingar. Studien granskar olika verktyg för tillämpningen. Därefter var Perfminer integrerat i Scanias Linux-kluster att profilera CFD och FEA-program som utnyttjar sats kösystem funktioner för kontinuerlig hela systemet profilering, vilket ger prestanda insikter för högpresterande tillämpningar, med försumbar overhead. Perfminer ger stabila, noggranna profiler och ett kluster skala verktyg för prestandaanalys. Perfminer belyser effektivt mikro arkitektoniska flaskhalsar.

Intelligent devices, interconnectivity, and information exchange are characteristics often associated with Industry 4.0. A peer-to-peer-oriented architecture with the network as the system center succeeds the traditional controller-centric topology used in today's distributed control systems, improving information exchange in future designs. The network-centric architecture allows IT-solution such as cloud, fog, and edge computing to enter the automation industry. IT-solution that rely on virtualization techniques such as virtual machines and containers. Virtualization technology, combined with virtual instance management, provide the famous elasticity that cloud computing offer. Container management systems like Kubernetes can scale the number of containers to match the service demand and redeploy containers affected by failures. Distributed control systems constitute automation infrastructure core in many critical applications and domains. The criticality puts high dependability requirements upon the systems, i.e., dependability is essential. High-quality software and redundancy solutions are examples of traditional ways to increase dependability. Dependability is the common denominator for the challenges addressed in this thesis. Challenges that range from concurrency defect localization with static code analysis to utilization of failure recovery mechanisms provided by container management systems in a control system context. We evaluate the feasibility of locating concurrency defects in embedded industrial software with static code analysis. Furthermore, we propose a deployment agnostic failure detection and role selection mechanism for controller redundancy in a network-centric context. Finally, we use the container management system Kubernetes to orchestrate a cluster of virtualized controllers. We evaluate the failure recovery properties of the container management system in combination with redundant virtualized controllers - redundant controllers using the proposed failure detection and role selection solution.

The advent of FinFET technology necessitates a shift towards early dynamic power awareness, not only for ASIC block designers but also for software engineers that develop code for those blocks. CMOS dynamic power is typically reduced by optimizing the RTL models in terms of switching activity and clock gating efficiency. There is not much to be done after a model is committed. Programmable blocks though, like the Phoenix 4 Digital Signal Processor(EMCA Ericsson Multi Core Architecture), can have a “second chance” for low power even after silicon is produced by efficient use of the software source code in order to impact the dynamic power metrics. This requires a "full-stack" of power awareness all the way from the DSP hardware model up to the software development IDE. This Thesis work aims at two goals. The first goal is to realize a prototype, encapsulated flow for the DSP software developers which connects software IDE entry point to the low level, complex hardware power analysis tools. The second goal is to demonstrate how software can be used as an auxiliary knob to exploit potential tradeoffs in order to improve the DSP's dynamic power metrics. This hypothesis is tested by rescheduling operations on the DSP's resources either manually or implicitly through the compiler. Moreover, a method to align and compare algorithms, when it is possible to tradeoff performance for power, is devised and the estimation results are compared against real silicon measurements. The results show that the developed analysis flow is reliable and very efficient for the given purpose, even for people who have limited knowledge about low level hardware to facilitate quick power exploration and profiling. This is mainly realized by a unique feature that associates specific lines in the source code with the toggling behavior of the hardware model while execution. Based on that, the tradeoffs between power and performance for several testcases are demonstrated at both the assembly and C levels with good correlation versus silicon. Overall, this work's outcome hints that the compiler and software teams have many options to consider in order to optimize dynamic power for products already in the field.

Embedded systems have become commonplace in today's society and their complexity and number of functions are steadily increasing. This can be attributed to the unceasing advances in the microprocessor technology and the continuous delivery of more powerful and power-efficient microprocessors, which, in turn, allows more elaborate software implementations. Consequently, there is a strong interest in finding methods and tools that support flexible and efficient development of embedded software. Since these qualities are typically attributed to component-based design it makes sense to develop new design techniques targeting embedded systems based on components. This thesis aims to adapt the traditional component-based design approach for development of embedded real-time software. Component-based design relies on the existence of consistent and coherent models of individual components that can be composed to model the whole system. However, it can be argued that the special characteristics of embedded systems make such modeling challenging. One reason is that embedded systems typically exhibit a strong integration between hardware and software, which leads to a need for a common design space, or at least the possibility to create consistent models of both hardware and software components of an embedded system. Another reason is that the majority of embedded systems can be viewed as real-time systems and therefore it is necessary to express timing requirements alongside functional properties in the model. In order to overcome these difficulties, we adopt a reactive perspective, in which the functionality of both hardware and software is described in terms of time-constrained reactions of reactive objects. This enables capturing the complete functionality of the system (hardware and software) along with timing requirements in a single model.The reactive view lies behind the modeling framework for embedded real-time systems and the component-based software design methodology presented in this thesis. The methodology allows both functional and timing properties of a system model to be preserved during implementation process by means of a seamless transition between a model and an implementation, whereas the modeling framework enables the developer to offer platform-independent correctness for real-time systems, provided that the software can be scheduled on a given hardware platform. Further, this thesis includes a case study, in which the methodology is used for designing a real-life system. The case study demonstrates the potential of the methodology to bring the benefits of classical component-based design to the realm of embedded systems. / ESIS