Thesis (M.S.)--Ohio University, March, 1985. / Title from PDF t.p.

Thesis (MTech (Electrical Engineering))--Peninsula Technikon, 2003. / Word processed copy. Summary in English. Includes bibliographical references (leaves 132-135). Also available online.

Submitted in fulfillment of the requirement for the Masters degree of Technology (MTech): Electrical Engineering, 2003 / Contemporary software-defined radio (SDR) is continuously changing and challenging the way traditional RF systems operate. Having more of a radio system’s operation in software enables further flexibility through the use of software manipulation. Due to practical limitations, however, it is not always feasible to have the entire radio system’s operations performed using software. Practical limitations, therefore, require that a SDR employs some form of RF front-end in order to interface the antenna signals and the signals prior to the data converters. As technology grows in support of SDR development, this hardware interface is becoming increasingly smaller. The problem with the rapid rate at which SDR developments are occurring is that RF hardware needs to change accordingly. Therefore, the RF hardware front-end can be seen as a non-standardised piece of equipment. To the designer, this means having to prototype in hardware in order to experiment with various types of SDR hardware front-ends. One of a SDR’s main attractions is the inherent property of software testability. Taking this fact into account, this thesis investigates the design and operation of a basic softwaredriven RF front-end emulator for a SDR. Basic prototype software models are identified and developed in order to test their performance within the emulator. The focus of the thesis, however, is geared toward the development of a software architecture that enables a high degree of interchangeability amongst the underlying modelled components. In the case of a SDR, the advantage of prototyping in software is in predicting the behaviour of a system prior to having to perform any physical developments. This property of software testability in the emulator can only fully be appreciated if a bench-mark system is used to evaluate the overall performance of the emulator. Therefore, a physical hardware setup is performed in order to test the basic aspects of the emulators operation. This evaluation is not meant as an exhaustive analysis of the emulator, but aims to highlight the overall performance of the emulated system against a typical physical system setup.

The HP2623 graphics terminal emulator is implemented on the PC for use with the Starbase graphics package provided on the departmental HP9000 series 500 computer system. This paper discusses the development and implementation of this emulator. A demonstration of its compatibility with Starbase is also provided along with a users' manual and a programmers' reference.

The breakdown of Dennard's transistor scaling has driven computing systems toward application-specific accelerators, which can provide orders-of-magnitude improvements in performance and energy efficiency over general-purpose processors. To enable the radical departures from conventional approaches that heterogeneous systems entail, research infrastructure must be able to model processors, memory and accelerators, as well as system-level changes---such as operating system or instruction set architecture (ISA) innovations---that might be needed to realize the accelerators' potential. Unfortunately, existing simulation tools that can support such system-level research are limited by the lack of fast, scalable machine emulators to drive execution. To fill this need, in this dissertation we first present a novel machine emulator design based on dynamic binary translation that makes the following improvements over the state of the art: it scales on multicore hosts while remaining memory efficient, correctly handles cross-ISA differences in atomic instruction semantics, leverages the host floating point (FP) unit to speed up FP emulation without sacrificing correctness, and can be efficiently instrumented to---among other possible uses---drive the execution of a full-system, cross-ISA simulator with support for accelerators. We then demonstrate the utility of machine emulation for studying heterogeneous systems by leveraging it to make two additional contributions. First, we quantify the trade-offs in different coupling models for on-chip accelerators. Second, we present a technique to reuse the private memories of on-chip accelerators when they are otherwise inactive to expand the system's last-level cache, thereby reducing the opportunity cost of the accelerators' integration.

No description available.

Thesis (Ph. D.)--Computing, Georgia Institute of Technology, 2008. / Committee Chair: Fujimoto, Richard; Committee Member: Ammar, Mostafa; Committee Member: Bader, David; Committee Member: Goldsman, David; Committee Member: Park, Haesun; Committee Member: Riley, George.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 99-104). Also available via the Internet.

Thesis (M.S.)--Ohio University, June, 1994. / Title from PDF t.p.

Thesis (M.S.)--Oregon State University, 2005. / Printout. Includes bibliographical references (leaves 38-40). Also available on the World Wide Web.