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A multiple-input-multiple-output, or MIMO, receiver receives multiple data streams in the same frequency band at the same time, significantly improving spectral efficiency. It has to preserve all the antenna aperture information and use it to deliver as many data streams as the antenna count. As the number of antennas increases, implementing a MIMO receiver system in the analog domain becomes difficult. A digital MIMO receiver architecture that digitizes all the antenna inputs on the element level offers multiple advantages. Digital MIMO signal processing is flexing and powerful. Complex space-time array processing is supported and so is digital array calibration. Therefore, the digital MIMO receiver architecture has become the most promising architecture for future massive MIMO systems. However, the digital MIMO receiver architecture has a disadvantage, namely that the spatial selectivity feature is missing in the RF/analog domain. At the target frequency band, multiple spatial signals can arrive at the antenna array at different power levels. Conventional spectral filtering is ineffective at in-band frequency so all the spatial signals have to co-exist in all the receiver elements and the following analog-to-digital converters (A/Ds). The instantaneous dynamic range required for these RF/analog and mixed-signal circuits will be limited by the strongest spatial signal on the upper bound, and the weakest spatial signal on the lower bound. A high instantaneous dynamic range requirement directly translates to high power consumption and high cost. Therefore, the recovery of spatial selectivity in the RF/analog domain is necessary. The first thrust toward recovering RF/analog spatial selectivity in a digital MIMO receiver is the scalable spatial notch suppression technique. Knowing the direction of a strong spatial blocker, a spatial notch, instead of beams, can be synthesized to the blocker direction to filter it out. This means that all the analog baseband outputs will show high conversion gains to signals from all directions but one, namely the blocker direction. In this way, high sensitivity is preserved in most directions to receiver multiple weak spatial signals simultaneously, which will be digitized, and separated in the digital domain. In the blocker direction, a low conversion gain filters the blocker out, preventing it from demanding high dynamic range for all of the RF/analog circuits and the A/Ds. In order to synthesize the scalable spatial notch, a spatial notch filter (SNF) is designed to provide lower input impedance in the blocker direction and high impedance in other directions. Using this spatially modulated impedance to load a current mode receiver leads to spatially modulated conversion gain. A transparent RF front-end translates this impedance to the antenna interface to achieve spatial notch suppression right at the antennas. A feedforward spatial notch canceler (FF SNC) uses the available isolated blocker information to improve spatial suppression ratio. The spatial notch suppression is scalable through a baseband node, allowing the tiling of multiple ICs on the same PCB for larger scale MIMO systems. A prototype receiver array was implemented with a 65nm CMOS process. Experimental results showed 32dB steerable spatial notch suppression, more than 19db of suppression inside the notch direction across all frequencies. In-band output-referred IP3 was improved from -10dBV to +24dBV, from outside to inside the notch direction, and IIP3 was also improved from +11dBm to +18dBm. Single-element equivalent double-sideband noise figure (NFDSB,eq) was 2.2 to 4.6dB across the 0.1 to 1.7GHz operating frequency range, also showing an improvement compared to other multi-antenna receivers at similar frequency ranges. A second thrust is an RF/analog arbitrary spatial filtering receiver. Instead of filtering out strong spatial blockers, a more general and robust way to recover spatial selectivity is to impose an arbitrary spatial response that adaptively equalizes the power levels of all the spatial signals. In this way, all the spatial signals should have the same power level when reaching the A/Ds, allowing the use of low-power A/Ds with low dynamic ranges, which are essential for the realization of the digital massive MIMO solution. Such an arbitrary spatial filtering response requires the ability to synthesize multiple spatial notches that can be independently steered, the depth of the notches free adjusted. In addition, a few performance metrics need to be improved based on the first work. Spatial suppression ratio was limited by the lack of magnitude control in the first work. In-band in-notch linearity performance was limited by the use of voltage mode gyrators that requires a band-limiting high-impedance node, which also limits spatial suppression bandwidth. Also, the antenna array dimensions scale inversely with operating frequency. So pushing the receiver array to work at higher frequency is also desired. Toward these goals, a 65nm CMOS prototype receiver array was implemented. Wideband current-mode receiver front-ends that consist of inverter-based LNTAs and passive mixers can work up to 3.1GHz. A baseband current-mode beamformer can synthesize virtual grounds at the output nodes in the target notch directions, providing not only an arbitrary spatial response but also an baseband input impedance that is also spatially modulated, allowing spatial filtering at the LNTA output nodes. Current mode operation avoids the use of band-limiting high impedance nodes for strong spatial signals, leading to superior linearity and wideband spatial suppression. This 4-element prototype measured more than 50dB of spatial suppression ratios with single-notch settings across all measured directions. Up to three notches can be synthesized, each of which can be independently steered and its depth freely adjusted. An in-band OIP3 of +34dBV was measured, 10dB higher than the first work, due to the current mode operation. A 20dB suppression bandwidth of 320MHz, or equivalently 64% was measured, more than 20× improvement than the first work, also due to the current mode operation. On a separate note, an ultra-wideband LNTA was also designed for an RF channelizing receiver work. This two-stage LNTA makes use of a gm-boosted current mirror structure to harness the linearity advantage of a current mirror, the low-noise input matching of the feedback structure, the high transconductance gain of a two-stage structure and an ultra-wideband input matching advantage of a gyrator. The implemented 65nm CMOS prototype is fully integrated, and provides 242mS peak transconductance gain over 0.6-9.6GHz operating frequency range. It achieves 4.5dB of NF and +6.5dBm of IIP3. In summary, RF/analog spatial selectivity can be recovered in innovative methods to relax the dynamic range requirement for all the RF/analog circuits together with the following A/Ds in a digital MIMO receiver. The scalable spatial notch suppression technique and the arbitrary spatial filtering technique allow the use of low-power A/Ds, which are essential for truly massive MIMO systems with manageable power consumption.

Thesis (Ph. D.)--Ohio State University, 2007. / Title from first page of PDF file. Includes bibliographical references (p. 128-136).

Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision feedback equalization. Parallelism which doubles the symbol rate can be realized by setting the first tap of the feedback filter to zero. A mixed-signal implementation has been chosen for the parallel MDFE, in which coefficients for the 9-tap feedback filter are adapted in the digital domain by 10-bit up/ down counters; 6-bit current mode D/A converters are used to convert digital coefficients to differential current signals which are summed with the forward equalizer (FE) output, and a flash A/D is used to make decisions and generate error signals for adaptation. In this thesis, a description of the parallel structure and the adaptation algorithm are presented with behavioral level verification. The circuit design and layout were carried out in HP 1.2um n-well CMOS process. The design of the high-speed counter and the current-mode D/A are discussed. HSPICE simulations show that a symbol rate of 100Mb/s for the feedback equalizer is readily achieved. / Graduation date: 1997

Decision feedback equalizer (DFE) is an effective method to remove inter-symbol interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE potentially offers higher speed, smaller die area, and lower power consumption when compared to their digital counterparts. Most of the available DFE equalizers were realized by using digital FIR filters preceded by a flash A/D converter. Both the FIR filter and flash A/D converter are the major contributers to the power dissipation. However, this project focuses on the analog IC implementations of the DFE to achieve high speed and low power consumption. In other words, this project gets intensively involved in the design of a large-input highly-linear voltage-to-current converter, the design of a high-speed low-power 6-bit comparator, and the design of a high-speed low-power 6-bit current-steering D/A converter. The design and layout for the proposed analog equalizer are carried out in a 1.2 pm n-well CMOS process. HSPICE simulations show that an analog DFE with 100 MHz clock frequency and 6-bit accuracy can be easily achieved. The power consumption for all the analog circuits is only about 24mW operating under a single 5V power supply. / Graduation date: 1997

The object of this research is to develop a solution for band-limited channels. Backplane channels and GPON channels are investigated to apply an equalization technique. Different lengths of backplane channels are measured with different signal speeds to investigate the channel performance. Also a GPON system with different fiber lengths is designed and set up in a lab to measure the BER performance. The GPON system utilizes a Fabry-Perot laser for the most economical solution. After the circuits are fabricated, they are inserted into the system to measure the performance of the channels with equalizers. Both the backplane and the GPON system show successful channel improvement in measured eye diagrams and BER. To expedite the procedure and eventually build an adaptive system which could be inserted and self-optimizing, we found it essential to monitor the output of the equalizer. A novel analog way to achieve this goal is suggested. All the equalizers mentioned in this dissertation have one summing node to add up all the values from VGAs. This structure is very efficient, but in the event that there are too many VGAs, it draws too much current through the one node. This issue is dealt with by the design of two nine tap equalizers, which are compared to assess the difference in performance between the unbalanced structure and the balanced structure.

Thesis (Ph. D.)--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 138-144).

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 106-110). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 119-124). Also available in electronic format on the Internet.