Thesis (M.App.Sc.) - Carleton University, 2006. / Includes bibliographical references (p. 119-122). Also available in electronic format on the Internet.

Thesis (Ph. D.)--University of Texas at Austin, 2004. / Supervisor: Brian L. Evans. Vita. Includes bibliographical references. Also available from UMI.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 107-109). Also available in electronic format on the Internet.

Electronic dispersion compensation (EDC) of intermodal dispersion on short multimode fiber (MMF) links operating at 40 Gb/s is investigated through system level simulations and the design of two analog integrated circuit (IC) equalizers. System simulations using worst-case MMF link models show the effectiveness of a 2-tap baud spaced finite impulse response (FIR) equalizer for 40-m links, and a second-order Tbaud/2 infinite impulse response (IIR) equalizer for 50-m links. An IIR filter topology suitable for IC implementation with double loops and multiple delay sections was developed. The 2-tap FIR and the IIR equalizer are implemented in UMC 0.13-um and STM 90-nm CMOS processes respectively. Measurements demonstrate the FIR and IIR equalizing 38-Gb/s and 30-Gb/s cable channels respectively. To the author's knowledge, the double-loop multi-delay IIR equalizer is the first integrated traveling-wave equalizer utilizing poles as a means of frequency boosting, contrasting the conventional FIR technique of utilizing zeros.

Electronic dispersion compensation (EDC) of intermodal dispersion on short multimode fiber (MMF) links operating at 40 Gb/s is investigated through system level simulations and the design of two analog integrated circuit (IC) equalizers. System simulations using worst-case MMF link models show the effectiveness of a 2-tap baud spaced finite impulse response (FIR) equalizer for 40-m links, and a second-order Tbaud/2 infinite impulse response (IIR) equalizer for 50-m links. An IIR filter topology suitable for IC implementation with double loops and multiple delay sections was developed. The 2-tap FIR and the IIR equalizer are implemented in UMC 0.13-um and STM 90-nm CMOS processes respectively. Measurements demonstrate the FIR and IIR equalizing 38-Gb/s and 30-Gb/s cable channels respectively. To the author's knowledge, the double-loop multi-delay IIR equalizer is the first integrated traveling-wave equalizer utilizing poles as a means of frequency boosting, contrasting the conventional FIR technique of utilizing zeros.

Thesis. 1976. B.S.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / Microfiche copy available in Archives and Engineering. / by Gustav Laub III. / B.S.

The IEEE 802.3aq standard recommends a multi-tap decision feedback equalizer be implemented to remove inter-symbol interference and additive system noise from data transmitted over a 10 Gigabit per Second (10 Gbps) multi-mode fiber-optic link (MMF). The recommended implementation produces a design in an analog process. This design process is difficult, time consuming, and is expensive to modify if first pass silicon success is not achieved. Performing the majority of the design in a well-characterized digital process with stable, evolutionary tools reduces the technical risk. ASIC design rule checking is more predictable than custom tools flows and produces regular, repeatable results. Register Transfer Language (RTL) changes can also be relatively quickly implemented when compared to the custom flow. However, standard cell methodologies are expected to achieve clock rates of roughly one-tenth of the corresponding analog process. The architecture and design for a parallel linear equalizer and decision feedback equalizer are presented. The presented design demonstrates an RTL implementation of 10 GHz filters operating in parallel at 625 MHz. The performance of the filters is characterized by testing the design against a set of 324 reference channels. The results are compared against the IEEE standard group s recommended implementation. The linear equalizer design of 20 taps equalizes 88 % of the reference channels. The decision feedback equalizer design of 20 forward and 1 reverse tap equalizes 93 % of the reference channels. Analysis of the unequalized channels in performed, and areas for continuing research are presented.

This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit architecture and topology and implements the circuit in 0.18-um CMOS to enable 10-Gb/sec serial baseband data transmission over FR-4 backplane and optical fibre. The ADFE overcomes the first feedback-loop latency challenge of traditional digital and mixed-signal DFEs by separating data re-timing from equalization and also eliminates the need for clock-recovery prior to decision-feedback equalization. The ADFE enables 10-Gb/sec decision-feedback equalization using a 0.18-um CMOS process, the first to do so to the author s knowledge. A tuneable current-mode-logic (CML) feedback-loop is designed to enable first post-cursor cancellation for a range of data-rates and to have external control over loop latency over variations in process, voltage and temperature. CML design techniques are used to minimize current consumption and achieve the required voltage swing for decision-feedback to take place. The all-analog equalizer consumes less power and area than comparable state-of-the art DFEs. The ADFE is used to compensate inter-symbol interference (ISI) for 20 inches of FR-4 backplane and 300 m of multi-mode fibre at 10-Gb/sec. The ADFE also extends the reach of single-mode fibre at 10-Gb/sec to 120 km. The work described in this dissertation advances the state-of-the-art in equalization solutions for multi-Gb/sec serial data transmission and can find applications in several of the 10-Gb/sec Ethernet standards that have been approved recently. The contributions of this work toward future research are also discussed.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 71-72).

Στα ασύρµατα δίκτυα η τεχνολογία MIMO-OFDM έχει ευρέως υιοθετηθεί µε στόχο την αύξηση του ρυθµού δεδοµένων σε υπηρεσίες υψηλής ποιότητας. Στο δέκτη ενός συστήµατος MIMO-OFDM ο υπολογισµός του µητρώου συντελεστών που χρειάζεται ο εξισωτής (equalizer) είναι ένα κρίσιµο σηµείο µε υψηλή υπολογιστική πολυπλοκότητα. Η καθυστέρηση που απαιτείται για την εκτέλεση του συγκεκριµένου υπολογισµού επηρεάζει άµεσα το ρυθµό περάτωσης (throughput) και την ποιότητα υπηρεσίας (QoS). Σε συστήµατα wi-fi (για παράδειγµα στο IEEE 802.11ac) στην αρχή κάθε πακέτου µεταδίδονται προσυµφωνηµένα σύµβολα, ώστε να εκπαιδεύσουν τον εξισωτή. Η συµβατική µέθοδος περιµένει να έρθουν όλα τα σύµβολα και στη συνέχεια υπολογίζει τοµητρώο του εξισωτή. Μια πιο πρόσφατη µέθοδος που αποσκοπεί στη µείωση της παραπάνω καθυστέρησης είναι ο προοδευτικός υπολογισµός του µητρώου του εξισωτή. Στη µέθοδο αυτή, γίνονται υπολογισµοί ανά σύµβολο εκπαίδευσης χωρίς να επηρεάζεται το τελικό αποτέλεσµα. Στα πλαίσια της διπλωµατικής υλοποιήθηκαν αρχιτεκτονικές υλικού για εξισωτές που αξιοποιούν την ανωτέρω µέθοδο και απεικονίστηκαν σε αναπτυξιακό σύστηµα µε FPGA. Επίσης, διερευνήθηκε ο ρόλος της αναπαράστασης των δεδοµένων στην πολυπλοκότητα του συστήµατος και βελτιστοποιήθηκαν οι σχετικές σχεδιαστικές παράµετροι, µε έµφαση στη χρήση της λογαριθµικής αριθµητικής. / In wireless networks, the MIMO-OFDM technology has been widely adopted in order to increase the data rate at high quality of service (QoS). In the receiver, the MIMO equalizer matrix calculation is an important part with high computational complexity. The delay of the matrix calculation affects directly the system throughput and QoS. In wi-fi systems (e.g. IEEE 802.11ac), training symbols are transmitted at the beginning of every frame, in order to train the equalizer. The conventional method waits all the training symbols to arrive before starting the calculations. A recent method proposes the progressive calculation of the equalizer matrix in order to decrease the processing delay. In this method, the equalizer matrix calculation starts upon receiving the first training symbol. The object of this thesis is the development of hardware architectures for equalizers that follow the progressive method and their implementation on FPGA. Furthermore, we analyzed the impact of the data representation on the system complexity and optimized the respective design parameters, using logarithmic number system.