Decision feedback equalizer (DFE) is an effective method to remove inter-symbol interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE potentially offers higher speed, smaller die area, and lower power consumption when compared to their digital counterparts. Most of the available DFE equalizers were realized by using digital FIR filters preceded by a flash A/D converter. Both the FIR filter and flash A/D converter are the major contributers to the power dissipation. However, this project focuses on the analog IC implementations of the DFE to achieve high speed and low power consumption. In other words, this project gets intensively involved in the design of a large-input highly-linear voltage-to-current converter, the design of a high-speed low-power 6-bit comparator, and the design of a high-speed low-power 6-bit current-steering D/A converter. The design and layout for the proposed analog equalizer are carried out in a 1.2 pm n-well CMOS process. HSPICE simulations show that an analog DFE with 100 MHz clock frequency and 6-bit accuracy can be easily achieved. The power consumption for all the analog circuits is only about 24mW operating under a single 5V power supply. / Graduation date: 1997

The object of this research is to develop a solution for band-limited channels. Backplane channels and GPON channels are investigated to apply an equalization technique. Different lengths of backplane channels are measured with different signal speeds to investigate the channel performance. Also a GPON system with different fiber lengths is designed and set up in a lab to measure the BER performance. The GPON system utilizes a Fabry-Perot laser for the most economical solution. After the circuits are fabricated, they are inserted into the system to measure the performance of the channels with equalizers. Both the backplane and the GPON system show successful channel improvement in measured eye diagrams and BER. To expedite the procedure and eventually build an adaptive system which could be inserted and self-optimizing, we found it essential to monitor the output of the equalizer. A novel analog way to achieve this goal is suggested. All the equalizers mentioned in this dissertation have one summing node to add up all the values from VGAs. This structure is very efficient, but in the event that there are too many VGAs, it draws too much current through the one node. This issue is dealt with by the design of two nine tap equalizers, which are compared to assess the difference in performance between the unbalanced structure and the balanced structure.

Thesis (Ph. D.)--Auburn University, 2008. / Abstract. Vita. Includes bibliographical references (p. 138-144).

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 106-110). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 119-124). Also available in electronic format on the Internet.

Thesis (M.App.Sc.) - Carleton University, 2006. / Includes bibliographical references (p. 119-122). Also available in electronic format on the Internet.

Thesis (Ph. D.)--University of Texas at Austin, 2004. / Supervisor: Brian L. Evans. Vita. Includes bibliographical references. Also available from UMI.

Thesis (M.App.Sc.) - Carleton University, 2007. / Includes bibliographical references (p. 107-109). Also available in electronic format on the Internet.

Thesis. 1976. B.S.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / Microfiche copy available in Archives and Engineering. / by Gustav Laub III. / B.S.

This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit architecture and topology and implements the circuit in 0.18-um CMOS to enable 10-Gb/sec serial baseband data transmission over FR-4 backplane and optical fibre. The ADFE overcomes the first feedback-loop latency challenge of traditional digital and mixed-signal DFEs by separating data re-timing from equalization and also eliminates the need for clock-recovery prior to decision-feedback equalization. The ADFE enables 10-Gb/sec decision-feedback equalization using a 0.18-um CMOS process, the first to do so to the author s knowledge. A tuneable current-mode-logic (CML) feedback-loop is designed to enable first post-cursor cancellation for a range of data-rates and to have external control over loop latency over variations in process, voltage and temperature. CML design techniques are used to minimize current consumption and achieve the required voltage swing for decision-feedback to take place. The all-analog equalizer consumes less power and area than comparable state-of-the art DFEs. The ADFE is used to compensate inter-symbol interference (ISI) for 20 inches of FR-4 backplane and 300 m of multi-mode fibre at 10-Gb/sec. The ADFE also extends the reach of single-mode fibre at 10-Gb/sec to 120 km. The work described in this dissertation advances the state-of-the-art in equalization solutions for multi-Gb/sec serial data transmission and can find applications in several of the 10-Gb/sec Ethernet standards that have been approved recently. The contributions of this work toward future research are also discussed.