It is well established that an effective way to schedule knowledge of results (KR) during practice to facilitate motor learning is to allow the learner to control their KR delivery, termed self-controlled KR, rather than imposing the same schedule on the learner without choice, termed yoked KR. The learning advantages of self-controlled KR schedules have been attributed to motivational influences and/or information-processing activities with numerous researchers favouring the motivational perspective in recent years. However, many findings currently exist that are difficult to reconcile using a (purely) motivational influences explanation. For this dissertation, three experiments were conducted that aimed to better understand the learning advantages of self-controlled KR schedules from an information-processing perspective. Chapter 2 of this dissertation provides further evidence that the learning benefits of self-controlled KR schedules depend on the option of completing the decision to receive KR after a motor response. The option of making the KR decision after a trial, rather than before a trial was suggested to allow the learner to request KR only when a comparison between estimated and actual error would maximize the informational value of the KR received. This in turn would be expected to strengthen one’s error detection capabilities. This was supported by retention and transfer data where a more accurate ability to estimate one’s performance in the absence of KR was found in the two self-controlled groups that were able to make a KR decision after a trial. In addition, open-ended questions regarding the strategies used for requesting KR during practice were administered at the midpoint and end of practice. An inductive thematic analysis (Chapter 3) of the self-reported KR strategies generated five themes and it was noted that strategy use changes as a function of practice. That is, the dominant strategy used during the first half of practice was different from that used during the second half of practice. Based on the results presented in Chapters 2 and 3, Chapter 4 provides evidence that the KR-delay interval is a critical time period for reaping the learning benefits of self-controlled KR schedules. Specifically, having participants engage in an interpolated activity during the KR-delay interval eliminated the effectiveness of self-controlled KR schedules for motor learning. It is argued that the interpolated activity interfered with the processing of response-produced feedback upon movement completion that are critical for determining whether receiving KR on a given trial would provide a meaningful learning experience. Lastly, Chapter 5 provides evidence that suggests the primary motor cortex (M1) may not have a significant role in the learning advantages of self-controlled KR schedules. However, a caveat of this conclusion is that the learning benefits of practicing with a self-controlled KR schedule were negligible. Taken together, the results presented in this dissertation suggest that informational factors associated with the processing of response-produced feedback and KR for the development of one’s error-detection capabilities, rather than motivational influences are more critical for the learning advantages of self-controlled KR schedules.

Shrinking minimum feature size in deep sub-micron has made fabrication of progressively faster devices possible. The performance of interconnects has been a bottleneck in determining the overall performance of a chip. A reliable high-speed communication technique is necessary to improve the performance of on-chip communication. Recent publications have demonstrated that use of multiple threshold voltages improves the performance of a bus significantly. The multi-threshold capture mechanism takes advantage of predictable temporal behavior of a tightly coupled bus to predict the next state of the bus early. However, Use of multiple threshold voltages also reduces the voltage slack and consequently increases the susceptibility to noise. Reduction in supply voltage exacerbates the situation. This work proposes a novel error detection and correction encoding technique that takes advantage of the high performance of the multi-threshold capture mechanism as well as its inbuilt redundancy to achieve reliable high-speed communication while introducing considerably less amount of redundancy as compared to the conventional methods. The proposed technique utilizes graph-based algorithms to produce a set of valid code words. The algorithm takes advantage of implicit set operations using binary decision diagram to improve the scalability of the code word selection process. The code words of many crosstalk avoidance codes including the proposed error detection and correction technique exhibit a highly structured behavior. The sets of larger valid code words can be recursively formed using the sets of smaller valid code words. This work also presents a generalized framework for scalable on-chip code word generation. The proposed CODEC implementation strategy uses a structured graph to model the recursive nature of an encoding technique that facilitates scalable CODEC implementation. The non-enumerative nature of the implementation strategy makes it highly scalable. The modular nature of the CODEC also simplifies use of pipelined architecture thereby improving the throughput of the bus.

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Having learned how to program bitwise operations, it is now time to flex our bit bashing muscles by investigating some creative ways to perform common programming functions.

In this thesis we discuss a formal approach to the design of concurrent error detection (CED) logic in field-programmable gate arrays (FPGAs). Single event upsets (SEUs) occurring in look-up table (LUT) configuration bits are considered as the fault model. Our approach involves representing the LUT network of the design implemented in the FPGA with constraints to model the presence of SEUs as a boolean formula in conjunctive normal form. A quantified boolean formula (QBF) based approach to designing CED logic based on parity check codes is found to be infeasible for designs of a realistic size. It is shown that a satisfiability (SAT) solver can be used to find variable assignments that indicate which circuit outputs can be corrupted by upset events in the specified fault model. An algorithm is presented to automatically generate a parity check code, which will identify with one clock cycle detection latency a malfunction caused by an SEU. The resulting parity check logic can be verified using a SAT solver and it is shown to require fewer LUT resources than duplication for most circuits. / Master of Applied Science (MASc)

The purpose of this study was to determine the effect of instrumental timbre preference and instrumental timbre on the error detection skills of undergraduate conducting students. The study sought to answer two specific questions: Is timbre preference, as determined by Gordon's (1984) <u>Instrumental Timbre Preference Test</u> (ITPT), a factor in the ability of undergraduate conducting students to detect errors in pitch in short melodies while viewing the score? Is the ability of undergraduate conducting students to detect pitch errors in melodic passages influenced by the instrumental timbres of the band ensemble? To answer these two questions, Gordon's ITPT and the researcher developed <u>Test of Timbre Effect</u> (TTE) were administered to 147 undergraduate conducting students in 11 colleges and universities in Virginia, North Carolina, and Tennessee. The TTE was designed to consist of seven different subtests, each intended to be administered to a different sample of homogeneous undergraduate conducting students. Each subtest consisted of 14 randomized test items, including two melodies designated as "target melodies" that differed only in timbre across the subtests. The effect of timbre preference, timbre, and the interaction of the two independent variables was determined by a 2 x 7 analysis of covariance (ANCOVA) of each target melody. Further analysis was conducted using a two-way multivariate analysis of covariance (MANCOVA). Results indicated that timbre preference, timbre, and the interaction of timbre preference and timbre did not have an effect on the ability of undergraduate conducting students to detect pitch errors in short melodic passages. / Ed. D.

The growing need in industrial applications of high-performance robots has led to designs of lightweight robot arms. However the light-weight robot arm introduces accuracy and vibration problems. The classical robot design and control method based on the rigid body assumption is no longer satisfactory for the light-weight manipulators. The effects of flexibility of light-weight manipulators have been an active research area in recent years. A new approach to correct the quasi-static position and orientation error of the end-effector of a manipulator with flexible links is studied in this project. In this approach, strain gages are used to monitor the elastic reactions of the flexible links due to the weight of the manipulator and the payload in real time, the errors are then compensated on-line by a control algorithm. Although this approach is designed to work for general loading conditions, only the bending deflection in a plane is investigated in detail. It is found that a minimum of two strain gages per link are needed to monitor the deflection of a robot arm subjected to bending. A mathematical model relating the deflections and strains is developed using Castigliano's theorem of least work. The parameters of the governing equations are obtained using the identification method. With the identification method, the geometric details of the robot arms and the carrying load need not be known. The deflections monitored by strain gages are fed back to the kinematic model of the manipulator to find the position and orientation of the end-effector of the manipulator. A control algorithm is developed to compensate the deflections. The inverse kinematics that includes deflections as variables is solved in closed form. If the deflections at target position are known, this inverse kinematics will generate the exact joint command for the flexible manipulator. However the deflections of the robot arms at the target position are unknown ahead of time, the current deflections at each sampling time are used to predict the deflections at target position and the joint command is modified until the required accuracy is obtained. An experiment is set up to verify the mathematical model relating the strains to the deflections. The results of the experiment show good agreement with the model. The compensation control algorithm is first simulated in a computer program. The simulation also shows good convergence. An experimental manipulator with two flexible links is built to prove this approach. The experimental results show that this compensation control improves the position accuracy of the flexible manipulator significantly. The following are the brief advantages of this approach: the deflections can be monitored without measuring the payload directly and without the detailed knowledge of link geometry~ the manipulator calibrates itself with minimum human intervention; the compensation control algorithm can be easily integrated with the existing uncompensated rigid-body algorithm~ it is inexpensive and practical for implementation to manipulators installed in workplaces.

Die Dissertation stellt eine neue Herangehensweise an die Lösung der Aufgabe der funktionalen Diagnostik digitaler Systeme vor. In dieser Arbeit wird eine neue Methode für die Fehlererkennung vorgeschlagen, basierend auf der Logischen Ergänzung und der Verwendung von Berger-Codes und dem 1-aus-3 Code. Die neue Fehlererkennungsmethode der Logischen Ergänzung gestattet einen hohen Optimierungsgrad der benötigten Realisationsfläche der konstruierten Fehlererkennungsschaltungen. Außerdem ist eins der wichtigen in dieser Dissertation gelösten Probleme die Synthese vollständig selbstprüfender Schaltungen. / In this dissertation concurrent checking by use of a complementary circuit for an 1-out-of-n Codes and Berger-Code is investigated. For an arbitrarily given combinational circuit necessary and sufficient conditions for the existence of a totally self-checking checker are derived for the first time.

This thesis describes the development of Dapper (`Determiner And PrePosition Error Recogniser'), a system designed to automatically acquire models of occurrence for English prepositions and determiners to allow for the detection and correction of errors in their usage, especially in the writing of non-native speakers of the language. Prepositions and determiners are focused on because they are parts of speech whose usage is particularly challenging to acquire, both for students of the language and for natural language processing tools. The work presented in this thesis proposes to address this problem by developing a system which can acquire models of correct preposition and determiner occurrence, and can use this knowledge to identify divergences from these models as errors. The contexts of these parts of speech are represented by a sophisticated feature set, incorporating a variety of semantic and syntactic elements. DAPPER is found to perform well on preposition and determiner selection tasks in correct native English text. Results on each preposition and determiner are discussed in detail to understand the possible reasons for variations in performance, and whether these are due to problems with the structure of DAPPER or to deeper linguistic reasons. An in-depth analysis of all features used is also offered, quantifying the contribution of each feature individually. This can help establish if the decision to include complex semantic and syntactic features is justified in the context of this task. Finally, the performance of DAPPER on non-native English text is assessed. The system is found to be robust when applied to text which does not contain any preposition or determiner errors. On an error correction task, results are mixed: DAPPER shows promising results on preposition selection and determiner confusion (definite vs. indefinite) errors, but is less successful in detecting errors involving missing or extraneous determiners. Several characteristics of learner writing are described, to gain a clearer understanding of what problems arise when natural language processing tools are used with this kind of text. It is concluded that the construction of contextual models is a viable approach to the task of preposition and determiner selection, despite outstanding issues pertaining to the domain of non-native writing.

Les blocs cryptographiques utilisés dans les circuits intégrés implémentent des algorithmes prouvés robustes contre la cryptanalyse. Toutefois des manipulations malveillantes contre le circuit lui-même peuvent permettre de retrouver les données secrètes. Entre autres, les attaques dites « en fautes » se sont révélés particulièrement efficaces. Leur principe consiste à injecter une faute dans le circuit (à l'aide d'un faisceau laser par exemple), ce qui produira un résultat erroné et à le comparer à un résultat correct. Il est donc essentiel de pouvoir détecter ces erreurs lors du fonctionnement du circuit.Les travaux de thèse présentées dans ce mémoire ont pour objet la détection concurrente d'erreurs dans les circuits cryptographique, en prenant comme support l'implantation du standard d'encryption symétrique l'Advanced Encryption standard « AES ». Nous analysons donc plusieurs schémas de détection d'erreur basés sur de la redondance d'information (code détecteur), certains issus de la littérature, d'autres originaux utilisant un double code de parité entrée-sortie permettant l'amélioration du taux de détection d'erreur dans ces circuits. Nous présentons aussi une étude montrant que le choix du type du code détecteur le plus approprié dépend, d'une part du type d'erreur exploitable pouvant être produite par un attaquant, et d'autre part du type d'implémentation du circuit à protéger. Les circuits cryptographiques sont également la cible d'autres attaques, et en particulier les attaques par analyse de consommation. Les contre mesures proposés jusqu'à lors pour un type d'attaques, se révèlent la plupart du temps néfastes sur la résistance du circuit face à d'autres types d'attaque. Nous proposons dans cette thèse une contre mesure conjointe qui protège le circuit à la fois contre les attaques en fautes et les attaques par analyse de consommation. / The cryptographic blocks used in the integrated circuits implement algorithms proved robust against cryptanalysis. However, malicious manipulation against the circuit itself can retrieve the secret data. Among known hardware attacks, attacks called "fault attacks" are proved particularly effective. Their principle is to inject a fault in the circuit (using for example a laser beam) that will produce an erroneous result and to compare it with a correct result. Therefore, it is essential to detect these errors during the circuit running.The work presented in this thesis concerns the concurrent detection of errors in cryptographic circuits, using as support the implementation of the Advanced Encryption Standard "AES". Thus, we analyze several error detection schemes based on the redundancy of information (detector code). We present a solution using dual code of parity to improve the rate of error detection in these circuits. We also present a study showing that the choice of the type of the detector code depends on one hand on the type of error that can be produced and be used by an attacker. On the other hand, it depends on type of the circuit implementation that we want to protect.The cryptographic circuits are also the target of further attacks, especially attacks by consumption analysis. The measures proposed against a type of attack, proved mostly negative against other types of attack. We propose in this work a joint measure that protects the circuit against both fault attacks and attacks by analysis of consumption.