Today's computer and network communication systems rely on authenticated and secure transmission of information, which requires computationally efficient and low bandwidth cryptographic algorithms. Among these cryptographic algorithms are the elliptic curve cryptosystems which use the arithmetic of finite fields. Furthermore, the fields of characteristic two are preferred since they provide carry-free arithmetic and at the same time a simple way to represent field elements on current processor architectures. Arithmetic in finite field is analogous to the arithmetic of integers. When performing the multiplication operation, the finite field arithmetic uses reduction modulo the generating polynomial. The generating polynomial is an irreducible polynomial over GF(2), and the degree of this polynomial determines the size of the field, thus the bit-lengths of the operands. The fundamental arithmetic operations in finite fields are addition, multiplication, and inversion operations. The sum of two field elements is computed very easily. However, multiplication operation requires considerably more effort compared to addition. On the other hand, the inversion of a field element requires much more computational effort in terms of time and space. Therefore, we are mainly interested in obtaining implementations of field multiplication and inversion. In this dissertation, we present several new bit-parallel hardware architectures with low space and time complexity. Furthermore, an analysis and refinement of the complexity of an existing hardware algorithm and a software method highly efficient and suitable for implementation on many 32-bit processor architectures are also described. / Graduation date: 1999

Graduation date: 1995

Balanced codes, in which each codeword contains equally many 1's and 0's, are useful in such applications as in optical transmission and optical recording. When balanced codes are used, the same number of 1's and 0's pass through the channel after the transmission of every word, so the channel is in a dc-null state. Optical channels require this property because they employ AC-coupled devices. Line codes, in which codewords may not be balanced, are also used as dc-free codes in such channels. In this thesis we present the research that leads to the following results: 1- Balanced codes These have higher information rate than existing codes yet maintain similar encoding and decoding complexities. 2- Error-correcting balanced codes In many cases, these give higher information rates and more efficient encoding and decoding algorithms than the best-known equivalent codes. 3- DC-Free coset codes A new technique to design dc-free coset codes was developed. These codes have better properties than existing ones. 4- Generalization of balanced codes -- Balanced codes are generalized in three ways among which the first is the most significant: a) Balanced codes with low dc level These codes are designed based on the combined techniques used in (1) and (3) above. A lower dc-level and higher transitions density is achieved at the cost of one extra check bit. These codes are much more attractive, to optical transmission, than the bare-bone balanced codes. b) Non-Binary Balanced Codes Balanced codes over a non-binary alphabet. c) Semi-Balanced Codes -- Codes in which the number of 1's and 0's in every code word differs by at most a certain value. 5- t-EC/AUED coset codes These are t error correcting/all unidirectional error detecting codes. Again the technique in (3) above is used to design t-EC/AUED coset codes. These codes obtain higher information rate than the best-known equivalent codes and yet maintain the same encoding/decoding complexity. / Graduation date: 1990

Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be lowered by using higher transmission power or by using an effective error correcting code. Power consumption and limits for electromagnetic radiation are two of the main problems with handheld devices today and an efficient error correcting code will lower the transmission power and therefore also the power consumption of the device. Duo-binary CTC is an improvement of the innovative turbo codes presented in 1996 by Berrou and Glavieux and is in use in many of today's standards for radio communication i.e. IEEE 802.16 (WiMAX) and DVB-RSC. This report describes the development of a duo-binary CTC decoder and the different problems that were encountered during the process. These problems include different design issues and algorithm choices during the design. An implementation in VHDL has been written for Alteras Stratix II S90 FPGA and a reference-model has been made in Matlab. The model has been used to simulate bit error rates for different implementation alternatives and as bit-true reference for the hardware verification. The final result is a duo-binary CTC decoder compatible with Alteras Stratix II designs and a reference model that can be used when simulating the decoder alone or the whole signal processing chain. Some of the features of the hardware are that block sizes, puncture rates and number of iterations are dynamically configured between each block Before synthesis it is possible to choose how many decoders that will work in parallel and how many bits the soft input will be represented in. The circuit has been run in 100 MHz in the lab and that gives a throughput around 50Mbit with four decoders working in parallel. This report describes the implementation, including its development, background and future possibilities.

This dissertation is mainly focused on the analysis, design and optimization of Low-density parity-check (LDPC) codes over channels with large alphabet sets and the applications on compressed sensing (CS) and flash memories. Compared to belief-propagation (BP) decoding, verification-based (VB) decoding has significantly lower complexity and near optimal performance when the channel alphabet set is large. We analyze the verification-based decoding of LDPC codes over the q-ary symmetric channel (q-SC) and propose the list-message-passing (LMP) decoding which off ers a good tradeoff between complexity and decoding threshold. We prove that LDPC codes with LMP decoding achieve the capacity of the q-SC when q and the block length go to infinity. CS is a newly emerging area which is closely related to coding theory and information theory. CS deals with the sparse signal recovery problem with small number of linear measurements. One big challenge in CS literature is to reduce the number of measurements required to reconstruct the sparse signal. In this dissertation, we show that LDPC codes with verification-based decoding can be applied to CS system with surprisingly good performance and low complexity. We also discuss modulation codes and error correcting codes (ECC’s) design for flash memories. We design asymptotically optimal modulation codes and discuss their improvement by using the idea from load-balancing theory. We also design LDPC codes over integer rings and fields with large alphabet sets for flash memories.

Thesis (M.S.)--West Virginia University, 2001. / Title from document title page. Document formatted into pages; contains vi, 68 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 67-68).

Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references. Available also from UMI/Dissertation Abstracts International.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2004. / Thesis advisor(s): Murali Tummala, Roberto Cristi. Includes bibliographical references (p. 133-134). Also available online.

Thesis (M. Phil.)--University of Hong Kong, 2010. / Includes bibliographical references (leaves 59-61). Also available in print.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Yucel Altunbasak. / Vita. Includes bibliographical references (leaves 141-146).