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A reconfigurable prototyping system for multiple-input multiple-output communicationsDalton, John January 2009 (has links)
Masters Research - Master of Engineering / This thesis demonstrates the process of building a system to test multiple-input multiple-output (MIMO) communications over-the-air. It covers the entire process, from concept to design and construction, culminating in transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK) and 2x2 Alamouti encoded BPSK modulation respectively. Finally, data packets are transmitted and measured BER performance curves constructed. Channel estimation is proved to work on a 2x2 MIMO channel over-the-air, the introduced loss of Eb/N0 shown to be approximately 0.5 dB compared to perfect channel information. The analogue limitations of the hardware are investigated and bit error rate performance measured as a function of operating point. Finally single antenna communications and a 2x2 Alamouti MIMO scheme are compared over-the-air, the Alamouti scheme delivering a 3 dB improvement in Eb/N0 performance. Satisfyingly the MIMO scheme also exceeds the best case theoretical performance bound of the single antenna case by a margin of 2 dB in Eb/N0.
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A reconfigurable prototyping system for multiple-input multiple-output communicationsDalton, John January 2009 (has links)
Masters Research - Master of Engineering / This thesis demonstrates the process of building a system to test multiple-input multiple-output (MIMO) communications over-the-air. It covers the entire process, from concept to design and construction, culminating in transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK) and 2x2 Alamouti encoded BPSK modulation respectively. Finally, data packets are transmitted and measured BER performance curves constructed. Channel estimation is proved to work on a 2x2 MIMO channel over-the-air, the introduced loss of Eb/N0 shown to be approximately 0.5 dB compared to perfect channel information. The analogue limitations of the hardware are investigated and bit error rate performance measured as a function of operating point. Finally single antenna communications and a 2x2 Alamouti MIMO scheme are compared over-the-air, the Alamouti scheme delivering a 3 dB improvement in Eb/N0 performance. Satisfyingly the MIMO scheme also exceeds the best case theoretical performance bound of the single antenna case by a margin of 2 dB in Eb/N0.
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Optimization algorithms for dynamically reconfigurable embedded systemsAhmadinia, Ali January 2006 (has links)
Zugl.: Erlangen, Nürnberg, Univ., Diss., 2006
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Kanalschätzung, Demodulation und Kanalcodierung in einem FPGA-basierten OFDM-FunkübertragungssystemTönder, Nico January 2007 (has links)
Zugl.: Hamburg, Techn. Univ., Diss., 2007
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55 |
Optimales Gatewaydesign mit genetischem Algorithmus und ganzzahliger linearer ProgrammierungHauer, Wolfgang, January 2008 (has links)
Ulm, Univ., Diss., 2008.
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Entwicklung eines MMI und Host-PC-Interface für einen HF/ZF-TransceiverSchönfeld, Martin. January 2004 (has links)
Konstanz, FH, Diplomarb., 2004.
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Occlusion culling and hardware accelerated volume renderingMeißner, Michael. Unknown Date (has links) (PDF)
University, Diss., 2000--Tübingen. / Erscheinungsjahr an der Haupttitelstelle: 2000.
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58 |
Preemptive Multitasking auf FPGA-Prozessoren ein Betriebssystem für FPGA-Prozessoren /Simmler, Harald C. Unknown Date (has links) (PDF)
Universiẗat, Diss., 2001--Mannheim.
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Evaluation of an FPGA and PCI bus based readout buffer for the Atlas experimentMüller, Matthias. Unknown Date (has links) (PDF)
University, Diss., 2005--Mannheim. / Erscheinungsjahr an der Haupttitelstelle: 2004.
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Optimization algorithms for dynamically reconfigurable embedded systems /Ahmadinia, Ali. January 2006 (has links)
Nürnberg, University, Diss., 2006--Erlangen.
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