In recent years, the state-of-the-art in field programmable gate array (FPGA) technology has been advancing rapidly. Consequently, the use of FPGAs is being considered in many applications which have traditionally relied upon application-specific integrated circuits (ASICs). FPGA-based designs have a number of advantages over ASIC-based designs, including lower up-front engineering design costs, shorter time-to-market, and the ability to reconfigure devices in the field. However, ASICs have a major advantage in terms of computational resources. As a result, expensive high performance ASIC algorithms must be redesigned to fit the limited resources available in an FPGA. <p> Concurrently, coaxial cable television and internet networks have been undergoing significant upgrades that have largely been driven by a sharp increase in the use of interactive applications. This has intensified demand for the so-called upstream channels, which allow customers to transmit data into the network. The format and protocol of the upstream channels are defined by a set of standards, known as DOCSIS 3.0, which govern the flow of data through the network. <p> Critical to DOCSIS 3.0 compliance is the upstream demodulator, which is responsible for the physical layer reception from all customers. Although upstream demodulators have typically been implemented as ASICs, the design of an FPGA-based upstream demodulator is an intriguing possibility, as FPGA-based demodulators could potentially be upgraded in the field to support future DOCSIS standards. Furthermore, the lower non-recurring engineering costs associated with FPGA-based designs could provide an opportunity for smaller companies to compete in this market. <p> The upstream demodulator must contain complicated synchronization circuitry to detect, measure, and correct for channel distortions. Unfortunately, many of the synchronization algorithms described in the open literature are not suitable for either upstream cable channels or FPGA implementation. In this thesis, computationally inexpensive and robust synchronization algorithms are explored. In particular, algorithms for frequency recovery and equalization are developed. <p> The many data-aided feedforward frequency offset estimators analyzed in the literature have not considered intersymbol interference (ISI) caused by micro-reflections in the channel. It is shown in this thesis that many prominent frequency offset estimation algorithms become biased in the presence of ISI. A novel high-performance frequency offset estimator which is suitable for implementation in an FPGA is derived from first principles. Additionally, a rule is developed for predicting whether a frequency offset estimator will become biased in the presence of ISI. This rule is used to establish a channel excitation sequence which ensures the proposed frequency offset estimator is unbiased. <p> Adaptive equalizers that compensate for the ISI take a relatively long time to converge, necessitating a lengthy training sequence. The convergence time is reduced using a two step technique to seed the equalizer. First, the ISI equivalent model of the channel is estimated in response to a specific short excitation sequence. Then, the estimated channel response is inverted with a novel algorithm to initialize the equalizer. It is shown that the proposed technique, while inexpensive to implement in an FPGA, can decrease the length of the required equalizer training sequence by up to 70 symbols. <p> It is shown that a preamble segment consisting of repeated 11-symbol Barker sequences which is well-suited to timing recovery can also be used effectively for frequency recovery and channel estimation. By performing these three functions sequentially using a single set of preamble symbols, the overall length of the preamble may be further reduced.

Soft computing techniques are generally well-suited for vehicular control systems that are usually modeled by highly nonlinear differential equations and working in unstructured environment. To demonstrate their applicability, two intelligent controllers based upon fuzzy logic theories and neural network paradigms are designed for performing a wall-following task and an autonomous parking task. Based on performance and flexibility considerations, the two controllers are implemented onto a reconfigurable hardware platform, namely a Field Programmable Gate Array (FPGA). As the number of comparative studies of these two embedded controllers designed for the same application is limited in the literature, one of the main goals of this research work has been to evaluate and compare the two controllers in terms of hardware resource requirements, operational speeds and trajectory tracking errors in following different pre-defined trajectories. The main advantages and disadvantages of each of the controllers are presented and discussed in details. Challenging issues for implementation of the controllers on the FPGA platform are also highlighted. As the two controllers exhibit benefits and drawbacks under different circumstances, this research suggests as well a hybrid controller scheme as an attempt to integrate the benefits of both control units. To evaluate its performance, the hybrid controller is tested on the same pre-defined trajectories and the corresponding results are compared to that of the fuzzy logic and the neural network based controllers. For further demonstration of the capabilities of the wall-following controllers in other applications, the fuzzy logic and the neural network controllers are used in a parallel parking system. We see this work to be a stepping stone for further research work aiming at real world implementation of the controllers on Application Specified Integrated Circuit (ASIC) type of environment.

As Field-Programmable Gate Array (FPGA) capacity can now support several processors on a single device, the scalability of FPGA design tools and methods has emerged as a major obstacle for the wider use of FPGAs. For example, logic synthesis, which has traditionally been the fastest step in the FPGA Computer-Aided Design (CAD) flow, now takes several hours to complete in a typical FPGA compile. In this work, we address this problem by focusing on two areas. First, we revisit FPGA logic synthesis and attempt to improve its scalability. Specifically, we look at a binary decision diagram (BDD) based logic synthesis flow, referred to as FBDD, where we improve its runtime by several fold with a marginal impact to the resulting circuit area. We do so by speeding up the classical cut generation problem by an order-of-magnitude which enables its application directly at the logic synthesis level. Following this, we introduce a guided partitioning technique using a fast global budgeting formulation, which enables us to optimize individual “pockets” within the circuit without degrading the overall circuit performance. By using partitioning we can significantly reduce the solution space of the logic synthesis problem and, furthermore, open up the possibility of parallelizing the logic synthesis step. The second area we look at is the area of Engineering Change Orders (ECOs). ECOs are incremental modifications to a design late in the design flow. This is beneficial since it is minimally disruptive to the existing circuit which preserves much of the engineering effort invested previously in the design. In a design flow where most of the steps are fully automated, ECOs still remain largely a manual process. This can often tie up a designer for weeks leading to missed project deadlines which is very detrimental to products whose life-cycle can span only a few months. As a solution to this, we show how we can leverage existing logic synthesis techniques to automatically modify a circuit in a minimally disruptive manner. This can significantly reduce the turn-around time when applying ECOs.

Soft computing techniques are generally well-suited for vehicular control systems that are usually modeled by highly nonlinear differential equations and working in unstructured environment. To demonstrate their applicability, two intelligent controllers based upon fuzzy logic theories and neural network paradigms are designed for performing a wall-following task and an autonomous parking task. Based on performance and flexibility considerations, the two controllers are implemented onto a reconfigurable hardware platform, namely a Field Programmable Gate Array (FPGA). As the number of comparative studies of these two embedded controllers designed for the same application is limited in the literature, one of the main goals of this research work has been to evaluate and compare the two controllers in terms of hardware resource requirements, operational speeds and trajectory tracking errors in following different pre-defined trajectories. The main advantages and disadvantages of each of the controllers are presented and discussed in details. Challenging issues for implementation of the controllers on the FPGA platform are also highlighted. As the two controllers exhibit benefits and drawbacks under different circumstances, this research suggests as well a hybrid controller scheme as an attempt to integrate the benefits of both control units. To evaluate its performance, the hybrid controller is tested on the same pre-defined trajectories and the corresponding results are compared to that of the fuzzy logic and the neural network based controllers. For further demonstration of the capabilities of the wall-following controllers in other applications, the fuzzy logic and the neural network controllers are used in a parallel parking system. We see this work to be a stepping stone for further research work aiming at real world implementation of the controllers on Application Specified Integrated Circuit (ASIC) type of environment.

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

The paper proposes a model of detection for voltages and harmonics using wavelet-probabilistic network (WPN). WPN is a two-layer structure, containing the wavelet layer and probabilistic network. It uses the wavelet transformation (WT) and probabilistic neural network (PNN) to analyze distorted waves and classify tasks. In this thesis, the field programmable gate array (FPGA) is employed for the hardware realization of WPN. In the implementation process, by the use of the hardware description language, the WPN algorithm has been embedded into the FPGA chip. Firstly, we divide the mathematical formula of basic WPN algorithm into several parts in order to set up each module individually, then we integrate all modules to complete the design of basic WPN algorithm with digital circuits by the bottom-up process.

ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / A field programmable gate array (FPGA) is used to decode Inter-Range Instrumentation Group (IRIG) time code for a PC-based Time-Space-Position Information (TSPI) acquisition. The FPGA architecture can latch time via an external event trigger or a programmable periodic internal event. By syncing time with an external IRIG Group Type B (IRIG-B) signal and using an 8 megahertz (MHz) internal clock, captured time has 125 nanosecond (ns) precision. A Range Instrumentation Control System (RICS) application utilizing the FPGA design to capture IRIG time is presented and test results show matching time accuracy when compared to commercial IRIG time capture hardware components.

Η μεγάλη εξάπλωση των δικτύων που βασίζονται στο Internet Protocol (IP) , έδωσε την ευκαιρία για χρήση του Διαδικτύου για μετάδοση φωνής , μέσω της τεχνολογίας Voice over IP(VoIP) , έναντι των παραδοσιακών δημοσίων τηλεφωνικών δικτύων (PSTN) . Το Session Initiation Protocol είναι το πρωτόκολλο σηματοδοσίας , που χρησιμοποιείται για τον έλεγχο συνόδων πολυμέσων , όπως κλήσεις φωνής ή βιντεοκλήσεις στα δίκτυα IP . Η χρησιμοποίηση του πρωτοκόλλου σε φορητές συσκευές , όπου η διαχείριση πόρων παίζει σπουδαίο ρόλο , δίνει το ερέθισμα για τη δημιουργία ειδικού υλικού που θα αποφορτίζει τον επεξεργαστή της συσκευής από τους απαιτητικούς ελέγχους που χρειάζονται για την δημιουργία μιας συνόδου . Στα πλαίσια της παρούσας διπλωματικής εργασίας παρουσιάζεται ένα σύστημα , υλοποιημένο σε FPGA , που προσομοιώνει έναν χρήστη SIP , κι έχει τη δυνατότητα να λαμβάνει , να επεξεργάζεται και να απαντά σε μηνύματα για την δημιουργία μια συνόδου . Στα κεφάλαια που ακολουθούν παρουσιάζεται η δομή του πρωτοκόλλου και τα χαρακτηριστικά του συστήματος που υλοποιήθηκε . Αρχικά παρουσιάζονται οι βασικές αρχές του πρωτοκόλλου και τα δομικά στοιχεία του . Έπειτα αναλύεται η δομή ενός SIP μηνύματος κι εξηγούνται οι λόγοι που κάνουν την αποθήκευσή του απαιτητική εργασία για την CPU . Έπειτα αναλύεται η βασική διαδικασία δημιουργίας συνόδου χρησιμοποιώντας ένα παράδειγμα . Το επόμενο μέρος αφιερώνεται στην αναλυτική περιγραφή του συστήματος που υλοποιήθηκε και την διαδικασία ελέγχου της ορθής λειτουργίας του . Τέλος παρουσιάζονται τα αποτελέσματα και συμπεράσματα της εργασίας . / The wide spread of networks based on Internet Protocol (IP), gave the opportunity for using the Internet for voice transmission , through Voice over IP (VoIP) technology, over traditional public telephone networks (PSTN). The Session Initiation Protocol is a signaling protocol , used to control multimedia sessions such as voice calls or video calls in IP networks. The use of this protocol in mobile devices , where resources management is very important ,is giving the stimulus for the creation of special hardware that offloads the CPU of demanding controls needed to create a session . As part of this thesis ,a system implemented on FPGA, which simulates a SIP user, and has the ability to receive, process and respond to messages to create a session , is presented. The following chapters present the structure of the protocol and the characteristics of the implemented system . Originally presented the basic principles of the Protocol and its structural elements . Thereafter the structure of a SIP message is analyzed , and the reasons that make storing a demanding work for the CPU , are explained. Then the basic process of creating a session is analyzed , using an example . The next part is devoted to a detailed description of the implemented system and the process of verifying the proper operation. Finally are presented the results and conclusions of the work .

Field-programmable gate arrays (FPGAs) have the potential to address scaling challenges in CMOS technology because of their regular structures and the flexibility they possess by being re-configurable after fabrication. One of the potential approaches in attacking scaling challenges, such as negative-bias temperature instability (NBTI) and process variation (PV), is by using placement techniques that are aware of these problems. Such techniques aim at placing a circuit in an FPGA such that the critical path delay is improved compared to the expected worst case. This can be achieved by placing NBTI-critical blocks of a circuit in areas with fast transistors in an FPGA chip. In this thesis, we present a detailed research effort that addresses the joint effect of NBTI and PV in FPGAs. We follow an experimental methodology in that we use actual PV data that we measure from 15 FPGA chips. The measured data is used to study the joint effect of NBTI and PV on the timing performance of circuits that are placed and routed in FPGAs. Enhancements are made to a well-known FPGA placement algorithm, T-VPlace, in order to make the placement process aware of the joint effect of NBTI and PV. Results are given for the placement and routing of Microelectronics Center of North Carolina (MCNC) benchmark circuits to show the effectiveness of the proposed techniques in addressing scaling challenges in FPGAs. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2009-09-24 17:23:29.626