A fully integrated, fast-locking fractional-N frequency synthesizer is proposed and demonstrated in this work. In this design, to eliminate the need for large, inaccurate capacitors and resistors in a loop filter, an analog continuous-time loop filter whose performance is sensitive to process and temperature variations and aging has been replaced with a programmable digital Finite Impulse Response (FIR) filter. In addition, using the adaptive loop gain control proportional to the frequency difference, the frequency-locking time has been reduced. Also, the phase noise and spurs have been reduced by a Multi-stAge noise SHaping (MASH) controlled Fractional Frequency Detector (FFD) that generates a digital output corresponding directly to the frequency difference. The proposed frequency synthesizer provides many benefits in terms of high integration ability, technological robustness, fast locking time, low noise level, and multimode flexibility. To prove performance of the proposed frequency synthesizer, the frequency synthesizers analysis, design, and simulation have been carried out at both the system and the circuit levels. Then, the performance was also verified after fabrication and packaging.

It has been aimed to investigate the complexity of discrete-coefficient FIR filters when they are implemented in transposed form and the coefficient redundancy is removed by the n-Dimensional Reduced Adder Graph (RAG-n) approach. Filters with coefficients represented by different quantization schemes have been designed or selected from the literture / their transposed form implemetations after RAG-n process have been compared in terms of complexity. A Genetic Algorithm (GA) based design algorithm has been implemented and used for the design of integer coefficient filters. Algorithms for the realization of filter coefficients in Canonic Signed Digit (CSD) form and realization of n-Dimensional Reduced Adder Graph (RAG-n) have also been implemented. Filter performance is measured as Normalized Peak Ripple Magnitude and implementation complexity as the number of adders used to implement filter coefficients. Number of adders used to implement filter coefficients is calculated by using two different methods: CSD and RAG-n. RAG-n method has been applied to FIR digital filter design methods that don&rsquo / t consider reduction of implementation complexity via RAG-n with transposed direct form filter structure. For implementation complexity, it is concluded that &ldquo / RAG-n algorithm with transposed direct form filter structure&rdquo / provides better results over the &ldquo / CSD, SPT coefficient design followed by transposed direct form filter structure&rdquo / in terms of number of adders used in the implementation.