De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque étape du cycle de conception. Le prototypage matériel sur une plateforme multi-FPGA présente le meilleur compromis entre le temps de conception d'un circuit et le temps d'exécution d'une application par ce circuit. Pour l'implémenter sur cette plateforme, une opération de partitionnement est effectuée avant de créer des partitions capables de s'intégrer dans chaque FPGAPar conséquent, des signaux coupés à l'interface des partitions doivent passer d'un FPGA à un autre. Cependant, le nombre de traces physiques inter-FPGA est limité ce qui crée des problèmes de routabilité du circuit prototypé. Cette thèse touche surtout la partie post-partitionnement et s'intéresse au problème deroutage inter-FPGA. Ainsi, les principaux travaux de cette thèse sont les suivants :Dans un premier temps, nous nous intéressons au développement d'un générateur debenchmarks qui permet, à l'aide d'une description architecturale simple du benchmark, de générer un circuit modélisé avec le langage de description matérielle VHDL. Le générateur utilise un ensemble de composants ce qui donne aux benchmarks un aspect réel semblable à celui des circuits industriels. Ces circuits de tests nous serviront pour évalue rles performances des techniques développées dans cette thèse. Dans un deuxième temps, nous proposons de développer un outil spécifique qui intervient après le partitionnement pour prendre en compte la contrainte liée à la limitation du nombre d'interconnexion entre les FPGAs. Cet outil est basé sur une approcheitérative visant à réduire le taux de multiplexage (nombre de signaux qui partagent un seul _l physique). Le routage en lui même est assuré par l'algorithme de routage Pathfinder adapté. Cet algorithme servira comme point de départ pour les techniques de routage développées durant cette thèse. Des adaptations adéquates seront faites pour cibler un ré-seau de routage inter-FPGA. Dans une deuxième partie, nous essayons de déterminer la meilleure forme du signal à router (bi-points ou multi-points) ainsi que le graphe de routage utilisé. Pour cela, nous proposons des scénarios de test a_n de sélectionner les critères qui donnent la fréquence de fonctionnement la plus performante. Par la suite, nous présentons une description détaillée des IPs de multiplexage utilisés.Ces IPs sont insérés dans les parties émettrices et réceptrices d'un canal de communication. Ces IPs incluent des composants spécifiques appelés SERDES pour assurer la sérialisation/déserialisation des données à transmettre. L'insertion de ces composants peut créer des problèmes de routabilité intra-FPGA. Ainsi, dans une deuxième partie, nous proposons un algorithme de placement basé sur l'estimation de la congestion afin d'améliorer la routabilité du circuit. / This thesis mainly deals with the post-partitioning task and addresses the problem of inter-FPGA routing. Thus, the main contributions of this thesis are: Firstly, we focus on the development of a benchmark generator which, using a simple architectural description of the benchmark, generates a circuit modelled with the hardware description language VHDL. The generator uses a set of industrial components providing benchmarks with real behaviour similar to that of industrial circuits. These benchmarks are used to evaluate the performance of the techniques developed in this thesis. In a second step , we propose a speci_c tool which acts after the partitioning to handle the constraints related to the limited number of interconnection between FPGAs. This tool is based on an iterative approach and aims to reduce the multiplexing ratio (the number of signals that share the same physical wire). The routing task itself is operated by the Pathfinder routing algorithm which is widely used by academic and industrial researchers . This algorithm is used as a starting point for routing techniques developed in this thesis . In a second part , we try to identify the best shape of the routed signals and the appropriate routing graph. For this reason, we propose scenarios to select criteria that give the best system frequency. Finally, we present a detailed description of the architecture of the multiplexing IPs. These IPs are inserted in the transmitting and receiving FPGAs of a communication channel. These IPs include speci_c components called SERDES for serialization/deserialization of the data. The insertion of these IPs can create problems of intra-FPGA routability. Thus, in a second part, we propose a placement algorithm based on congestion estimation to improve the routability of the circuit.

Reconfigurable circuits (Field Programmable Gate Arrays (FPGAs)) for accelerating applications have been a key technology for many years. Thus, the world’s leading data center operators and providers of cloud infrastructures, namely Microsoft, IBM, and soon Amazon, are using FPGAs on their application platforms. The central question of this contribution is how FPGAs can be virtualized for a flexible and dynamic deployment in cloud infrastructures. In addition to the virtualization of FPGA resources, service models for the provision of virtualized FPGAs are developed and embedded into a resource management system in order to evaluate the cloud system’s behaviour. The objective of this work is not to build a cloud architecture, but rather to examine selected aspects of cloud systems with regard to the integration of reconfigurable hardware. The FPGAs are not only virtualized but, unlike in many other projects, the entire system and the application are taken into account. As a result, the vFPGAs are used dynamically and adaptively at different locations and topologies in the cloud architecture, depending on the user’s requirements. Furthermore, a prototypical implementation of a cloud system has been developed, and evaluated in several projects. The virtualization using state-of-the-art FPGAs has shown that the establishment of homogenous environments is possible. The Migration of a partial FPGA context is also possible with current FPGA architectures, but is associated with high costs in form of hardware resources. Furthermore, a simulation was carried out to determine whether virtualization and migration, could contribute to a more efficient utilization of resources in a larger cloud system or impair the service level agreement. In summary, both the developed virtualization and the possibility of a migration make it possible to reduce the amount of necessary resources in a modern cloud system. / Rekonfigurierbare Schaltkreise wie Field Programmable Gate Arrays (FPGAs) stellen seit Jahren für viele Unternehmen eine Schlüsseltechnologie zur Hintergrundbeschleunigung von Anwendungen und Cloud- Diensten dar. Als weltweit führende Betreiber von Rechenzentren und Anbieter von Cloud-Infrastrukturen setzten mittlerweile Microsoft, IBM und demnächst auch Amazon in ihren Systemen FPGAs auf Anwendungsebene ein, um sowohl die Rechenleistung zu erhöhen als auch die Verlustleistung und damit die Betriebskosten zu reduzieren. Ebenso stellt die Erhöhung der Zugangssicherheit durch Nutzung von FPGAs einen weiteren bedeutenden Aspekt dar. Die zentrale Fragestellung dieser Arbeit besteht darin, wie FPGAs durch Virtualisierung effizient auf der Anwendungsebene nutzbar gemacht werden können. Das Ziel besteht darin, die FPGAs wie andere Komponenten flexibel und dynamisch in der Cloud einzusetzen. Um ein Cloud-System mit FPGAs evaluieren zu können, werden zunächst Servicemodelle für eine Bereitstellung der virtualisierten FPGAs entwickelt und in eine Ressourcenverwaltung eingebettet. Ziel der Arbeit ist hierbei nicht der Aufbau einer Cloud-Architektur selbst, sondern vielmehr die Untersuchung ausgewählter Aspekte mit Hinblick auf die Integration rekonfigurierbarer Hardware in eine Cloud. Dabei wird die klassische System-Virtualisierung auf die rekonfigurierbare Hardware übertragen, um eine Abstraktion vom physischen FPGA zu erreichen und diesen möglichst effizient auslasten zu können. Das Ziel besteht hierbei darin, mehrere unabhängige, nebenläufig arbeitende Nutzerkerne auf demselben physischen FPGA zu realisieren und durch Migration auf andere Rechenknoten zu übertragen sowie von der physischen Größe und der Architektur des FPGAs zu abstrahieren. Dabei wird nicht nur der FPGA virtualisiert, sondern – anders als bei der Mehrzahl vergleichbarer Arbeiten – das Gesamtsystem und der Einsatzzweck berücksichtigt. Ein prototypisch entwickeltes Cloud-System wurde im Rahmen mehrerer Projekte evaluiert. Durch diese prototypische Umsetzung wird nachgewiesen, dass eine FPGA-Virtualisierung auf aktuellen FPGAs möglich ist und welche Kosten dazu erforderlich sind. Ebenso zeigt sich, dass aufgrund bestimmter fester Strukturen eine Etablierung von homogenen Bereichen notwendig ist, um die Migration eines partiellen FPGA-Kontextes zu ermöglichen und eine effiziente Lastverteilung in der Cloud zu realisieren. Die prototypische Implementierung zeigt, dass eine Migration mit aktuellen FPGA-Architekturen möglich, aber mit Kosten in Form von FPGA-Ressourcen verbunden ist. Des Weiteren wird mittels Simulation untersucht, ob die in einem komplexen Anwendungsszenario angewendete Migration auch in einem größeren Cloud-System zu einer effizienteren Auslastung der Ressourcen beitragen kann. Zusammenfassend ist sowohl durch die entwickelte Virtualisierung als auch durch die Möglichkeit einer Migration die Einsparung von Hardware-Ressourcen und somit auch Energie in einem modernen Cloud-System möglich.

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores - Major Telecomunicações. Faculdade de Engenharia. Universidade do Porto. 2013

Orientador: Furio Damiani / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-15T03:48:46Z (GMT). No. of bitstreams: 1 Bernardo_Rodrigo_M.pdf: 3176872 bytes, checksum: a6a7b540ec1bfd0dbe839744ef1adf5e (MD5) Previous issue date: 2009 / Resumo: Este trabalho apresenta o desenvolvimento e a prototipagem de um nó de acesso utilizado como prova de conceito de redes de chaveamento de pacotes ópticos. Ele descreve as arquiteturas propostas para a rede e o nó de acesso, juntamente com o desenvolvimento detalhado do hardware, desde a concepção até os testes finais dos módulos (placas), e do núcleo de processamento implementado em dispositivo de lógica programável, que constitui a inteligência da rede. O nó de acesso foi concebido de forma modular, com quatro módulos desenvolvidos para compor o elemento principal da rede, cada um com tecnologia e função especifica. O trabalho também descreve os testes realizados com os protótipos, demonstrando que os requisitos inicialmente propostos foram alcançados / Abstract: This work presents the development and prototyping of an access node for an optical packet switching network. The network's architecture and the access node proposals are described, as well as the detailed hardware development, from the conception to modules' (boards) final tests and core processing implemented on PLDs, which constitutes the intelligence of the network. The access node was conceived in a modular way, with four modules developed to compose the main element of the network, each with its proper technology and function. The work also describes the tests performed on the prototypes, showing that the proposed requirements were met / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Orientadores: Dalton Soares Arantes, Fabbryccio Akkazzha Chaves Machado Cardoso / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-15T17:04:47Z (GMT). No. of bitstreams: 1 Moreira_VeruskaRodrigues_M.pdf: 1358124 bytes, checksum: b78b10c0a05e8732e9f54ceb1cbbdceb (MD5) Previous issue date: 2009 / Resumo: Esta dissertação apresenta a concepção e o desenvolvimento de uma plataforma em hardware reconfigurável denominada REDLART - REconfigurable Digital Laboratory for Advanced Research and Teaching, visando soluções de laboratório a distância aplicadas ao ensino e ao trabalho colaborativo em sistemas digitais. A plataforma é baseada em dispositivos FPGA (Field Programmable Gate Array) para desenvolvimento de circuitos digitais com aplicações em processamento digital de sinais, sistemas de comunicações digitais, sistemas de controle e áreas afins. Além da plataforma de hardware, também foi concebida e implementada uma arquitetura de sistema, composta por um conjunto de softwares cliente-servidor, com o objetivo de viabilizar o acesso remoto através da gerência e da configuração de experimentos desenvolvidos na REDLART. Tal sistema, incluindo a própria REDLART, possibilita o desenvolvimento de novos experimentos e sua disponibilização na Web, resultando em um WebLab reconfigurável para sistemas digitais. Testes foram realizados em nível de hardware e software para a validação da plataforma / Abstract: This thesis presents a reconfigurable hardware platform called REDLART (REconfigurable Digital Laboratory for Advanced Research and Teaching), designed to enable laboratory applications in distance learning and collaborative work in digital systems. The platform is based on FPGA devices (Field Programmable Gate Array) to develop digital circuit applications for digital signal processing, digital communication systems, control systems and related areas. Besides the hardware platform, a system architecture consisting of a set of client-server software was also designed and implemented in order to enable the remote access through the management and configuration of experiments developed in REDLART. By using the client-server software with the REDLART platform, new experiments can be developed and made available on the Web, resulting in a WebLab for reconfigurable digital systems. Tests were performed at the hardware and software levels for the validation of the platform / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

Nowadays the ever increasing algorithmic complexity of embedded applications requires the designers to turn towards heterogeneous and highly integrated systems denoted as SoC (System-on-a-Chip). These architectures may embed CPU-based processors, dedicated datapaths as well as recon gurable units. However, embedded SoCs are submitted to stringent requirements in terms of speed, size, cost, power consumption, throughput, etc. Therefore, new computing paradigms are required to ful l the constraints of the applications and the requirements of the architecture. Recon gurable Computing is a promising paradigm that provides probably the best trade-o between these requirements and constraints. Dynamically recon gurable architectures are their key enabling technology. They enable the hardware to adapt to the application at runtime. However, these architectures raise new challenges in SoC design. For example, on one hand, designing a system that takes advantage of dynamic recon guration is still very time consuming because of the lack of design methodologies and tools. On the other hand, scheduling hardware tasks di ers from classical software tasks scheduling on microprocessor or multiprocessors systems, as it bears a further complicated placement problem. This thesis deals with the problem of scheduling online real-time hardware tasks on Dynamically Recon gurable Hardware Devices (DRHWs). The problem is addressed from two angles : (i) Investigating novel algorithms for online real-time scheduling/placement on DRHWs. (ii) Scheduling/Placement algorithms library for RTOS-driven Design Space Exploration (DSE). Regarding the first point, the thesis proposes two main runtime-aware scheduling and placement techniques and assesses their suitability for online real-time scenarios. The first technique discusses the impact of synthesizing, at design time, several shapes and/or sizes per hardware task (denoted as multi-shape task), in order to ease the online scheduling process. The second technique combines a looking-ahead scheduling approach with a slots-based recon gurable areas management that relies on a 1D placement. The results show that in both techniques, the scheduling and placement quality is improved without signi cantly increasing the algorithm time complexity. Regarding the second point, in the process of designing SoCs embedding recon gurable parts, new design paradigms tend to explore and validate as early as possible, at system level, the architectural design space. Therefore, the RTOS (Real-Time Operating System) services that manage the recon gurable parts of the SoC can be re fined. In such a context, gathering numerous hardware tasks scheduling and placement algorithms of various complexity vs performance trade-o s in a kind of library is required. In this thesis, proposed algorithms in addition to some existing ones are purposely implemented in C++ language, in order to insure the compatibility with any C++/SystemC based SoC design methodology.

Orientador: Peter Jurgen Tatsch / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T19:07:29Z (GMT). No. of bitstreams: 1 Monte_LuisRenato_M.pdf: 9957740 bytes, checksum: 0889b0686d62fd3269d4a48322410bf6 (MD5) Previous issue date: 2009 / Resumo: Este trabalho apresenta as especificações arquitetônicas e funcionais de uma rede ótica avançada, fundamentada na comutação óptica de rajadas e que objetiva um melhor aproveitamento dos enlaces ópticos e a redução do gargalo eletrônico decorrente das conversões eletro-ópticas. Uma proposta de concepção do núcleo de processamento de dados baseado em dispositivos lógicos programáveis e o projeto dos circuitos utilizados na etapa experimental, que compreendem uma placa comercial e três placas desenvolvidas serão apresentadas. Este trabalho tem como escopo apresentar uma nova arquitetura de rede de chaveamento de rajadas ópticas, seu princípio de funcionamento e a estrutura do nó de chaveamento óptico. É proposta uma estrutura para o núcleo de processamento de dados e apresentado o protótipo desenvolvido para a prova de conceito. / Abstract: This work presents the architectural and functional specifications of a new optical network, based on optical burst switching that aims at the better use of optical links and the reduction of the bottleneck resulting from electro-optics conversions. A proposed design of the core data-processing based on programmable logic devices and design of circuits used in the experimental stage, which include a business board and three boards developed exclusively for this project, will be presented. This work aims to present a new architecture for an optical burst switching network, its basic operation and the structure of an optical switching node. The data processing core structure is proposed and the circuitry prototypes developed to do the proof of concept are presented. / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-11T08:21:02Z (GMT). No. of bitstreams: 1 Pimenta_ValdineyAlves_M.pdf: 5178774 bytes, checksum: 75a2335b2db0969f79ae380d7479bff2 (MD5) Previous issue date: 2008 / Resumo: Contrariando as projeções para crescimento da economia mundial, o mercado de semicondutores cresce de forma acelerada, a uma taxa superior a 10% ao ano, movimentando anualmente mais de 270 bilhões de dólares. Acompanhando este crescimento, a importação de componentes eletrônicos pelo Brasil é um dos ítens que mais contribuem negativamente em sua balança comercial, deixando claro que o país não tem atuado de forma econômicamente interessante neste mercado. Um consórcio formado por 8 das principais universidades brasileiras, chamado BrazilIP, foi criado tendo como principal intuito inserir o Brasil no seleto grupo de países produtores de artefatos em semicondutores, em especial, na produção de componentes na forma de propriedade intelectual (IPs). Este grupo tem alcançado considerável sucesso ao longo dos últimos anos e é o foco da presente dissertação. O autor, que participou dos três primeiros anos de vida deste consór.cio, buscou registrar, na forma de método, as propostas, cursos, documentos e experiências ocorridas durante seu envolvimento. São também apresentados casos reais de aplicação da metodologia no desenvolvimento de um decoder de áudio MP3 e um codificador RSA. Uma das intenções deste trabalho é evitar que todo o conhecimento, adquirido e gerado pelo consórcio, se volatilize, além de permitir, através deste registro e exemplos de seu uso, que o método seja facilmente reaplicado em outras instituições de pesquisa. Somando-se a estas contribuições, didáticas e documentais, a dissertação ainda analisa vários pontos, positivos e negativos, sobre sua utilização e pioneirismo, propondo complementações e aprimoramentos / Abstract: Contrary to the projections ofthe worldwide economy's growth rate, the semiconductor market, estimated in 270 billions of dollars, grows over 10% each year. The electronic components market in Brazil has been growing at the same rate and poses a huge payout for the country in this area, leading to efforts in semiconductor training. The Brazil-IP consortium, formed by 8 of the major universities in Brazil, was created to try to insert the .country into the select group of countries that design semiconductors, focusing on intellectual property (IP) market. This group has achieved a considerable success over the past years and the systematization of its methodology is the focus of this dissertation. The contributions of this work are divided into three groups: (1) It registers the methodology in a reproducible way since the proposals, courses, documents and experiences that took place during the fist years were not put together. Since the author participated in the first three years, he is one of the recommended persons to do that. (2) It also exemplifies the methodology with real case studies, MP3 decoder and RSA, which is small enough to be used as first case exercise for new designers to be trained. (3) Finally it comments, makes suggestions and analyses the positive and negative points of the methodology as applied in the Institute of Computing, proposing enhancements and complementation / Mestrado / Sistemas de Computação / Mestre em Ciência da Computação

Orientador: Luís Geraldo Pedroso Meloni / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-19T09:59:52Z (GMT). No. of bitstreams: 1 Sousa_EriclesRodrigues_M.pdf: 2046025 bytes, checksum: 14fd32eefec8c8da68e3337d5e033567 (MD5) Previous issue date: 2011 / Resumo: Atualmente, aplicações multimídias exigem grande esforço computacional para manipular dados com elevadas taxas de precisão. Visando otimizar a capacidade de processamento sem elevar demasiadamente o custo do desenvolvimento em sistemas embarcados, este trabalho descreve a proposta de uma arquitetura computacional hibrida, para processamento digital de sinais, baseado-se no uso cooperativo entre DSP (Digital Signal Processor) e FPGA (Field Programmable Gate Array). Neste estudo e realizada uma abordagem sobre o uso de um coprocessador para a acelerar rotinas que demandam grande esforço computacional em um DSP. Também e proposto um modelo matemático capaz de mensurar a eficiência do particionamento de códigos processados de forma descentralizada. Para validação da proposta, foi construído um cenários de testes para a estimação de vetores movimento, um dos principais agentes envolvidos no processo de codificação de vídeo em alta definição. A partir do cenário elaborado foi possível constatar a eficiência da arquitetura proposta. Sendo que, considerando um código de referencia otimizado e baseado na descrição feita em [30], obteve-se mais de 97% de eficiência computacional. Assim, este estudo permite concluir que o uso cooperativo entre DSP e FPGA se mostra muito vantajoso devido a possibilidade de unir em um único sistema as vantagens fornecidas por ambos dispositivos, caracterizando um ambiente de total sinergia e de elevada capacidade de computacional / Abstract: Nowadays, multimedia applications require high computational effort to manipulate data with high precision. In order to optimize the processing power without significantly increasing the cost of development in embedded systems, this work describes the proposal for a hybrid computing architecture applied to digital signal processing, based on the cooperative work between DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array). An approach about the use of coprocessor able to accelerate a process which requires great computational effort of a DSP is provided by this study. It is also describes a mathematical model able to measure the efficiency of a partitioning code processed in a distributed system. To validate our proposal we developed a tested for calculate the motion estimation vector, which is one of key elements involved on high definition video coding. From the elaborated tested, we could found a high efficiency provided by the architecture proposed. Therefore, considering a optimized reference code based on [30], was possible achieve a computing efficiency around 97%. This study show that cooperative work between DSP and FPGA that provides a very advantageous scenario applied to embedded systems, due to joining the features of both devices, building then, a synergy environment of high computing performance / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

Orientador: Eurípedes Guilherme de Oliveira Nóbrega / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica / Made available in DSpace on 2018-08-20T08:18:33Z (GMT). No. of bitstreams: 1 Pagano_DaniloMorais_M.pdf: 25950218 bytes, checksum: f9af4571e3d7f1f88caed4d997e809ba (MD5) Previous issue date: 2012 / Resumo: Esta dissertação apresenta um sistema para processamento digital de sinais através de dispositivos de hardware reconfigurável. Uma implementação do algoritmo FFT foi adotada como meio para avaliar o desempenho da arquitetura proposta para o sistema. O processamento digital de sinais tradicionalmente tem um alto custo computacional, pois os algoritmos são implementados em software, o que pode não atender as restrições de tempo de aplicações reais. O objetivo principal deste trabalho é desenvolver uma arquitetura para adquirir os sinais através de módulos de aquisição de dados distribuídos em uma rede e processá-los usando um FPGA. Um microcontrolador da FreeScale Semiconductors'MARCA REGISTRADA' foi adotado como módulo de aquisição de dados, executando um sistema operacional de tempo real (RTOS) para garantir os requisitos temporais. Foi implementado o processador soft-core NIOS 2 da Altera'MARCA REGISTRADA' executando também um RTOS com recursos de comunicação em rede, incluindo um periférico escrito em VHDL para o processamento da FFT usando uma estrutura de pipeline baseada em estágios e comunicação direta ao barramento do processador. A versão em hardware do algoritmo obteve uma redução de até 2000 vezes no tempo de processamento da FFT comparado com a mesma versão implementada em software, alcançando um tempo de processamento de 3.9 microssegundos para sinais discretizados em 256 pontos, quando usado 100MHz de clock. A quantidade de pontos pode ser facilmente aumentada alterando-se apenas o núcleo do periférico desenvolvido, e os resultados permitem adotar a arquitetura proposta para aplicações em tempo real de processamento digital de sinais / Abstract: This work presents a digital signal processing system based on reconfigurable hardware. Implementation of the FFT algorithm is used as a mean to assess the adopted configuration performance. Digital signal processing algorithms are in general software implemented, incurring high computational cost, which may not attend the real-time constraints of real applications. The main objective of this work is to develop an FPGA based architecture to process signals acquired through a distributed network of data acquisition modules. A microcontroller from FreeScale Semiconductors'TRADE MARK' was adopted as data acquisition module, running a real-time operating system (RTOS) to guarantee timing requirements. The soft-core processor NIOS 2 from Altera'TRADE MARK' , also running an RTOS with network communication capabilities, was implemented including a peripheral module written in VHDL for the computation of the FFT, which uses a pipeline-based stage structure and directly communicates with the processor bus. The hardware version of the algorithm achieved a reduction up to 2000 times in the FFT processing time compared to the same version implemented in software, reaching a processing time of 3.9 microseconds for 256 points sampled signals when using 100MHz of clock. The number of points can be easily increased just changing the core of the developed peripheral module, and the results permit to expect adequate real-time application of digital signal processing adopting the proposed configuration / Mestrado / Mecanica dos Sólidos e Projeto Mecanico / Mestre em Engenharia Mecânica