Meta-analytic reliability generalizations (RGs) are limited by the scarcity of reliability reporting in primary articles, and currently, RG investigators lack a method to quantify the impact of such nonreporting. This article introduces a stepwise procedure to address this challenge. First, the authors introduce a formula that allows researchers to estimate the lower bound population average reliability for a desired instrument. Second, they present an equation to determine the Fail-Safe N for RG. This equation estimates the number of ''file drawer'' studies required to drop the aggregate score reliability of an instrument below a specified criterion value. Finally, the authors demonstrate the utility of these equations using published RG studies. Comments on the conclusions drawn from each RG application are provided.

aLes techniques utilisées pour la réalisation de systèmes électroniques destines au contrôle/commande d'applications critiques sont généralement basées sur le concept de la logique fail-safe conventionnelle. Bien qu'elles aient été largement éprouvées, ces techniques s'avèrent maintenant de plus en plus mal adaptées à la conception de systèmes de plus en plus complexes puisqu'elles font appel à des composants discrets spécifiques. C'est dans ce contexte que cette étude essaie d'évaluer la contribution des circuits intégrés autotestables, et plus spécialement les circuit self-checking (capables de détecter instantanément leurs propres erreurs), à la réalisation de systèmes intégrés à haute sureté de fonctionnement. Les travaux présentés dans cette thèse se proposent d'élargir la théorie des systèmes fail-safe aux circuits intégrés combinatoires. Comme application, nous étudions la faisabilité d'une interface autotestable hors-ligne capable de transformer les données des circuits autotestables en-ligne (self-checking) en signaux surs adaptes au pilotage d'éléments électrons mécaniques. Cette interface autorise la réalisation de circuits Vlsi strongly fail-safe qui sont susceptibles, dans les années à venir, de tenir une place de premier ordre dans le domaine des automatismes intégrés de sécurité. Toutes les considérations pratiques pour la conception de ces circuits sont basées sur des hypothèses de pannes analytiques liées à la technologie utilisée, ici le CMOS

Chaque actionneur d'un système sécuritaire doit être contrôlé par un signal sûr en présence de défaillance (fail-safe), c'est-à-dire qu'en cas de défaillance son état est soit correct, soit sûr. Les systèmes intégrés auto-contrôlables en ligne (self-checking) fournissent des groupes de signaux codés en sortie. Ces groupes de signaux ne permettent pas d'assurer le contrôle direct des actionneurs, car chaque actionneur est contrôlé par un seul signal qui doit être individuellement sûr. A cause de cette exigence particulière, il n'était pas possible d'implémenter en VLSI toutes les parties : un système auto contrôlé (self-checking) ou tolérant aux pannes (qui utilise par exemple un code détecteur d'erreur, une technique de duplication, triplication ou un processeur codé), et une interface fail-safe utilisant des composants discrets. Cette interface transforme les sorties du système de traitement en signaux fail-safe. Outre l'inconvénient des interfaces à composants discrets d'être très encombrantes et coûteuses, la probabilité de défaillance est augmentée et la durée de vie (MTTF) du système est diminuée dans ce cas par rapport à l'implémentation VLSI, ce qui limite la disponibilité du système. Il est donc intéressant d'intégrer en VLSI les interfaces fail-sage, capables d'assurer le contrôle sécuritaire des actionneurs. Dans ce mémoire, nous présentons une interface sécurisée de puissance réalisée en technologie de puissance intelligente. Cette interface transforme les signaux de contrôles codés en fréquence en signaux de puissance pour le contôle sécuritaire des actionneurs dans les transports ferroviaires. Elle repose sur l'utilisation du concet de fail-safe, et d'autocontrôlable pour atteintre un haut niveau de sécurité.

<p>  </p> <p>Many engineering structures are designed to withstand a critical mechanical load before failure. When a load greater than the critical load is encountered, the manner of structural failure is important. Nature has been a source of technical inspiration for centuries, and the power of modern scientific investigative techniques has enhanced engineers’ abilities to learn from millennia of evolutionary mechanical refinement. </p> <p>Chitons, a family of marine mollusks, feed on algae attached to rocky substrates, and parts of their feeding organs are subjected to varied loads in the process. In this work, the manner of failure of a chiton’s tooth and supporting structure is investigated, and it is suggested that mechanical details of the structure enable load-limiting and fail-safe performance that protects the animal from potentially dangerous overloading.</p>

International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Missile Flight Test Safety Managers (MFTSM) and other flight safety personnel at White Sands Missile Range (WSMR) constantly monitor the realtime space position of missile and airborne target vehicles and the telemetered missile and target vehicle performance parameters during the test flight to determine if these are about to leave Range boundaries or if erratic vehicle performance might endanger Range personnel, Range support assets or the nearby civilian population. WSMR flight safety personnel rely on the vehicle telemetry system to observe the Flight Termination System (FTS) parameters. A realtime closed loop that involves the ground command-destruct transmitter, the vehicle command-destruct receiver (CDR), other FTS components, the missile S-band telemetry transmitter, and the ground telemetry acquisition/ demultiplex system is active when the vehicle is in flight. The FTS engineer relies upon telemetry to provide read-back status of the flight termination system aboard the vehicle. WSMR flight safety personnel use the telemetry system to assess realtime airborne vehicle systems performance and advise the MFTSM. The MFTSM uses this information, in conjunction with space position information provided by an Interactive Graphics Display System (IGDS), to make realtime destruct decisions about missiles and targets in flight. This paper will aid the missile or target developer in understanding the type of vehicle performance data and FTS parameters WSMR flight safety personnel are concerned with, in realtime missile test operations.

<div>Due to recent advances in sensor technology and the exponential increase in computation power of electronic control units (ECUs) along with their increasing affordability, active safety and vehicle automation have become major trends in the commercial vehicle industry. New regulations for increased safety are also a major driver behind the industry's increased interest in that topic. As a result, being a crucial part of vehicle automation, steering systems had to be adapted to enable Active Steering. Consequently, commercial vehicle steering designers introduced the concept of torque and angle overlay using an electric motor in series with the conventional hydraulic steering system. However, despite the fact that these systems are becoming more prevalent in the market, they still suffer from inefficiencies intrinsic to the conventional hydraulic steering system still being used. These inefficiencies are a result of</div><div>flow metering losses due to the use of control valves to regulate the pump flow output, as well as inside the steering gear with the use control valves to build assistance pressure.</div><div><br></div><div><div>In this research project, we investigate the potential use of the proven pump Displacement Control (DC) technology in steering on-highway commercial vehicles. DC pumps have been shown to signicantly improve system efficiency as they allow the removal of control valves typically used to regulate </div><div>ow [1]. Instead, the displacement of the pump can be directly controlled to vary the pump's flow rate and direction,</div><div>and thus eliminating throttling losses. The DC technology has been successfully used in a steer-by-wire conguration for an articulated frame steering vehicle and has been shown to signicantly improve efficiency and productivity, as well as result in a reduction in fuel consumption [2].</div></div><div><br></div><div><div>In this work, we propose a steer-by-wire system, using DC pump technology, for on-highway commercial vehicles, and present the dierent possible congurations in which it can be implemented. Moreover, the benets and drawbacks of the steer-by-wire system are researched and identied. Subsequently, the system is designed and validated in simulation, on laboratory test setup, as well as on a test vehicle to prove its feasibility.</div></div><div><br></div><div><div>Chief among the drawbacks of the steer-by-wire system is potential failures that can lead to the complete loss of the steering function of the vehicle. As a result, different possible fail-safe mechanisms are researched from which the most suitable ones are proposed to allow the steer-by-wire system to fail safely. Moreover, two of the proposed fail-safe mechanism are implemented onto the test vehicle to prove and validate their feasibility.</div></div><div><br></div><div><div>Furthermore, an alternative way of using displacement controlled pumps for active steering is be proposed. For this concept, we investigate the possibility of actively controlling the driver's steering effort by varying the pump displacement while maintaining the mechanical link between the steering wheel and the road wheels. If successful, this method will allow for a more efficient way of providing steering assistance as it does away with the conventional control valves used to build pressure and regulate pump flow, and thus eliminating throttling losses. This method has also the advantage of having an intrinsic fail-safe mechanism with manual steering being always possible should the hydraulic or electric systems fail.</div></div>

No description available.

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.

Si on veut assurer de fawn efficace les tests de conception, de fabrication, de maintenance et le test accompli au cours de l'application pour les systemes electroniques, on est amend a integrer le test hors-ligne et le test en-ligne dans des circuits. Ensuite, pour que les systemes complexes tirent profit des deux types de tests, une telle unification doit etre &endue du niveau circuit aux niveaux carte et module. D'autre part, bien que rintegration des techniques de test hors-ligne et en-ligne fait qu'il est possible de concevoir des systemes pour toute application securitaire, le materiel ajoute pour assurer une haute siirete de fonctionnement fait que la fiabilite de ces systemes est reduite, car la probabilite d'occurrence de fautes augmente. Confront& a ces deux aspects antagoniques, cette these se fixe l'objectif de trouver un compromis entre la securite et la fiabilite de systemes electroniques complexes. Ainsi, dans un premier temps, on propose une solution aux problemes de test hors-ligne et de diagnostic qui se posent dans les &apes intermediaires de revolution vers les cartes 100% compatibles avec le standard IEEE 1149.1 pour le test "boundary scan". Une approche pour le BIST ("Built-In Self-Test") des circuits et connexions "boundary scan" illustre ensuite retape ultime du test hors-ligne de cartes. Puis, le schema UBIST ("Unified BIST") - integrant les techniques BIST et "self-checking" pour le test en-ligne de circuits, est combine au standard IEEE 1149.1, afin d'obtenir une strategie de conception en vue du test unifie de connexions et circuits montes sur des cartes et modules. Enfin, on propose un schema tolerant les fautes et base sur la duplication de ces modules securitaires qui assure la competitivite du systeme resultant du point de vue de la fiabilite, tout en gardant sa silrete inherente. / On one hand, if the goal is to ensure that the design validation, the manufacturing and the maintenance testing, along with the concurrent error detection are efficiently performed in electronic systems, one is led to integrate the off-line and the on-line testing into circuits. Then, for complex systems to make profit of these two types of tests, such unification must be extended from the circuit to the board and module levels. On the other hand, although the unification of off-line and on-line testing techniques makes possible the design of systems suiting any safety application, the hardware added for increasing the application safety also decreases the system reliability, since the probability of occurrence of faults increases. Faced to these two antagonist aspects, this thesis aims at finding a compromise between the safety and the reliability of complex electronic systems. Thus, firstly we propose a solution to the off-line test and diagnosis problems found in the intermediate steps in the evolution towards boards which are 100% compliant with the IEEE standard 1149.1 for boundary scan testing. An approach for the BIST (Built-In Self-Test) of boundary scan circuits and interconnects then illustrates the ultimate step in the board off-line testing. Next, the UBIST (Unified BIST) scheme - merging BIST and self-checking capabilities for circuit on-line testing, is combined with the IEEE standard 1149.1, in order to obtain a design strategy for unifying the tests of interconnects and circuits populating boards and modules. Finally, we propose a fault-tolerant scheme based on the duplication of these kind of modules which ensures the competitivity of the resulting system in terms of reliability at the same time as preserving the inherent module safety.