Orientador: Paulo Sollero / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Mecânica / Made available in DSpace on 2018-08-19T07:37:21Z (GMT). No. of bitstreams: 1 Panosso_GustavoBigolotti_M.pdf: 12522576 bytes, checksum: a2770608080caac37863b37dea341c66 (MD5) Previous issue date: 2011 / Resumo: O objetivo deste trabalho é realizar uma análise numérica dos critérios de falha para materiais compósitos laminados. Critérios de falha tradicionais, como os critérios de Tsai- Hill e Tsai-Wu, são estudados e comparados com critérios de falha mais recentes, baseados em fenômenos físicos, como os critérios de Puck e LaRC03. Dois envelopes de falha, Tensão Longitudinal pela Tensão Transversal e Tensão Transversal pela Tensão de Cisalhamento são implementados para cada um dos critérios estudados seguindo os moldes do World- Wide Failure Exercise (WWFE). Realiza-se também um estudo da variação da resistência longitudinal em função da orientação das fibras em laminados unidirecionais. Através do software comercial de elementos finitos ABAQUS, desenvolve-se uma rotina iterativa para se avaliar a falha em modelos laminados segundo as diferentes teorias de falha estudadas. O comportamento do material e seus respectivos modos de falha são investigados para cada caso. Uma discussão sobre as vantagens e desvantagens de cada critério e um parecer sobre qual teoria de falha se mostrou mais vantajosa é apresentada / Abstract: This work aims to perform a numerical analysis of failure criteria for composite laminated materials. Traditional failure criteria, such as the Tsai-Hill and Tsai-Wu, are studied and compared to recent failure criteria based on physical phenomenas, such as Puck and LaRC03 criteria. Two failure envelopes, Longitudinal Stress by Transverse Stress and Transverse Stress by Shearing Stress are implemented for each criterion in accordance with the World-Wide Failure Exercise (WWFE). It also presents a study of the longitudinal strength variation depending on the fiber orientation in unidirectional laminates. Through the commercial finite element software ABAQUS, a script is presented to evaluate the failure in laminated models due to the different failure theories studied. The material behavior and its respective failure modes are investigated for each case. A discussion of the advantages and disadvantages of each failure theory is also presented / Mestrado / Mecanica dos Sólidos e Projeto Mecanico / Mestre em Engenharia Mecânica

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In chip level testing using hardware description language approach, a difficult question to answer is: What is the best micro-operation perturbation for modeling fault at the chip level? In this thesis, an automatic evaluation system is developed to determine the best micro-operation perturbation. The measure used is the gate level stuck-at fault coverage achieved by the tests derived to cover the micro-operation perturbation faults. For small combinational circuits, it is shown that perturbing the elements into the logic dual is a good choice. For large combinational circuits, it is shown that there is very little variation in the gate level coverage achieved by the various microoperation faults. In this case, if coverage is to be improved, the micro-operation perturbation method must be augmented by other techniques. / Master of Science

Microprocessors are used in many applications where a high degree of reliability is required. For instance, satellite based systems operating in space have no way being serviced if something were goes wrong. Often these systems, operating in radiation environments, are subject to random high energy particles that pass through the device and upset the operation of the microprocessor for a short period but leave no permanent damage. These transient faults are difficult to predict, prevent, or detect but can lead to a system failure if not discovered. / Master of Science

A large number of errors in digital systems are due to the presence of transient faults. This is especially true of microprocessor-based systems working in a radiation environment that experience transient faults due to single event upsets. These upsets cause a temporary change in the state of the system without any permanent damage. Because of their random and non-recurring nature, transient faults are difficult to detect and isolate, hence they become a source of major concern, especially in critical real-time application areas. Concurrent detection of these errors is necessary for real-time operation. Most existing fault tolerance schemes either use redundancy to mask effects of transient faults or monitor the system for abnormal operations and then perform recovery operation. Although very effective, redundancy schemes incur substantial overhead that makes them unsuitable for small systems. Most monitoring schemes, on the other hand, only detect control flow errors. A new approach called Concurrent Processor Monitoring for on-line detection of transient faults is proposed that attempts to achieve high error coverage with small error detection latency. The concept of the execution profile of an instruction is defined and is used for detecting control flow and execution errors. To implement this scheme, a watchdog processor is designed for monitoring operation of the main processor. The effectiveness of this technique is demonstrated through computer simulations. / Ph. D.

In this thesis, methods of identification of redundant faults and test pattern compaction are presented. The aim of the research is to improve an existing test pattern generator ATALANTA by incorporating methods for identification of redundant faults and test compaction. The faults are modeled as stuck-at faults for combinational circuits. To guarantee the completeness of the generated test set all redundant faults should be identified. For this purpose, the process of dynamic unique sensitization is implemented. This process studies the circuit for the existing state of value assignments and determines the dynamic dominators to identify redundant faults. The test set size is compacted to reduce the test storage space and test application time. The process of compaction is done by shuffling the test set and simulating the re-arranged test set to drop unnecessary test patterns. Experimental results show that the methods lead to a smaller test set size and identification of all redundant faults. / Master of Science

The detection and location of faults on power transmission lines is essential to the protection and maintenance of a power system. Most methods of fault detection and location rely on measurements of electrical quantities provided by current and voltage transformers. These transformers can be expensive and require physical contact with the monitored high voltage equipment. In this work, current transformers were replaced by magnetic field sensing coils. Such coils can be located remotely from substations and switching stations and do not require physical contact with the conductors. Rather than observing each individual conductor, the use of the magnetic field sensors allows the monitoring of the transmission line condition using a collective quantity. This study explores the use of the magnetic field sensors as an alternative measurement device for fault detection and location.

This dissertation proposes several simple, robust, and non-intrusive condition monitoring methods for induction motors fed by closed-loop inverters and claw-pole generators with built-in rectifiers. While the flexible energy forms synthesized by power electronic converters greatly enhance the performance and expand the operating region of induction motors and claw-pole generators, they also significantly alter the fault behavior of these electric machines and complicate the fault detection and protection. In this dissertation, special characteristics of the connected closed-loop inverter and rectifier have been thoroughly analyzed, with particular interest in their impact on fault behaviors of the induction motor and the claw-pole generator. Based on the findings obtained from the theoretical and experimental analysis, several sensorless thermal, mechanical, and insulation monitoring methods are proposed by smartly utilizing special features and capabilities of the connected power electronic converter. A simple and sensitive stator turn-fault detector is proposed for induction motors fed by closed-loop inverter. In addition, a stator thermal monitoring method based on active DC current injection and direct voltage estimation is also proposed to prevent the closed-loop controlled induction motors from thermally overloading. The performance of both methods is demonstrated by extensive experimental results. Methods to detect serpentine belt slip, serpentine belt defect, rotor eccentricity have been proposed for claw-pole generators using only the available electric sensor information. Methods to detect and protect stator turn faults in claw-pole generators are also presented in this dissertation. Lastly, a novel method to detect the generalized bearing roughness fault is proposed. All the proposed condition monitoring techniques have been validated by experimental results.

In this thesis, several heuristics that aim to improve the performance of parallel fault simulation for synchronous sequential circuits have been investigated. Three heuristics were incorporated into a well known parallel fault simulator called PROOFS and the efficiency of the heuristics were measured in terms of the number of faults simulated in parallel, the number of gate evaluations, and the CPU time. The three heuristics are critical path tracing, dynamic area reduction and a new heuristic called two level simulation. Critical path tracing and dynamic area reduction which have been previously proposed for combinational circuits are extended for synchronous sequential circuits in this thesis. The two level simulation that was investigated in this thesis is designed for sequential circuits. Experimental results show that critical path tracing is the most effective of the three heuristics. In addition to the three heuristics, new fault injection and fault ordering methods were suggested to improve the speed of an efficient fault simulator called HOPE. HOPE, which was developed at Virginia Tech is, an improved version of PROOFS. HOPE_NEW, which incorporates the two heuristics performs better than HOPE in the number of gate evaluations and the CPU time. HOPE_NEW is about 1.13 times faster than HOPE for the ISCAS89 benchmark circuits. For the largest circuit, the speedup is about 40 percent. / Master of Science