Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 79-83). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 209-214). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 78-79). Also available via the Internet.

Thesis (M.S.)--University of Wisconsin--Madison, 1977. / eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 135-136).

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 86-87). Also available via the Internet.

The current technology used for location of permanent faults in high voltage direct current (HVDC) transmission lines and cables is based on the travelling-wave principle. This technology has served well for the conventional point-to-point HVDC systems, but is inadequate to handle emerging HVDC transmission configurations such as schemes with very long overhead lines or cables, schemes with a combination of cable and overhead line segments, and multi-terminal HVDC (MTHVDC) schemes. This research investigated accurate and economical ways to locate the faults on dc transmission lines in the aforementioned emerging HVDC transmission configurations. The accuracy of travelling-wave based fault location methods is highly dependent on the accuracy of measuring the time of arrival of the fault generated travelling waves. Investigations showed that post-processing of detection signals such as the line terminal voltages or surge capacitor currents with continuous wavelet transform yields consistent and accurate fault location results. This method was applied for fault location in HVDC systems with extra-long overhead lines and cables using only the terminal measurements. Simulation results verified the effectiveness of this method in locating the faults in a 2400 km long overhead line and a 300 km long underground cable. A new algorithm was proposed to locate the faults in a two-terminal HVDC system consisting of multiple segments of overhead lines and cables, using only the terminal measurements. Application of the proposed algorithm was analysed through detailed simulations. Correct performance was verified under various scenarios. A new algorithm was developed for locating the faults in a star-connected MTHVDC network. This algorithm is also required only the terminal measurements. Its effectiveness was verified through detailed simulations. Finally, a novel measurement scheme for detection of travelling-wave arrival times was proposed. A prototype of this measurement scheme which uses a Rogowski coil to measure the transient currents through the surge capacitors at the line terminals was implemented. Its effectiveness was validated through field tests in a real HVDC transmission system. The proposed measurement scheme could capture significantly clean signals in an actual substation environment, confirming the practicability of implementing the proposed new algorithms.

This research presents an analysis of the improvement in the performance of a class of fault tolerant multistage interconnection networks. In the network discussed here, fault tolerance is achieved by providing multiple redundant paths between the source and destination. The extra paths are obtained by providing redundant links between switching elements within a stave (intra-stage links), thereby increasing the switching element complexity. The techniques used in the construction of this network, its properties, advantages, and disadvantages are discussed. While early studies focused their effort in analyzing the fault tolerant characteristics of the network and the performance in a circuit switched environment, this investigation complements the previous work by examining fie performance of a packet switched network. The reasons for the choice of the architecture that include factors like hardware complexity, cost and simplicity of control algorithm are analyzed. The study concentrates on improving the run-time performance of the fault tolerant network. by using these multiple paths not only in the presence of a fault, but also in a fault-free environment. The throughput of the packet switched network in the presence of a fault, congestion and when fault free are analyzed. A description of the investigation, assumptions and factors used for the study, a cost analysis, and the results of the simulation analyses is included. / Master of Science

An overview of an existing hierarchical reconfiguration scheme for a fault-tolerant two-dimensional cellular architecture is presented, wherein an array of finite state machine cells controls the processing and switching elements. This allows the array to either reconfigure in the presence of faults, or to perform different processing functions. Since the control mechanism is distributed, the system is not subject to single-point "hard core" failures, as in the case of a global control mechanism. Unlike other fault-tolerant systems, the proposed method does not assume the existence of components which never fail. The processing elements in the array are logically connected in a mesh pattern, and are provided with additional physical connections to other cells. A local reconfiguration scheme allows faulty cells to be bypassed via these additional connections, so that the logical mesh can be restored. This technique allows the array to quickly reconfigure in the presence of up to triple faults. When local reconfiguration fails, the array can still reconfigure by using a global reconfiguration scheme, in which the functional part of the array relocates itself to a faultfree area. The process is "global" in the sense that the entire functional part of the array is involved in the process, but the mechanism to accomplish this is still distributed in nature. With the framework of the system established, the results of this research are presented. The hardware complexities of the existing global reconfiguration scheme are analyzed, and compared with the complexities of previous work in this area. A distributed diagnosis algorithm is also developed, which works in conjunction with the local reconfiguration mechanism to quickly detect and isolate faults in the array. Using these results, the foundations are laid for a totally self-checking implementation of the control cells, which allows online concurrent fault detection in the array. / Master of Science

published_or_final_version / Mechanical Engineering / Doctoral / Doctor of Philosophy

Fault Recovery in process control requires effective fault detection, diagnosis and recovery schemes, and a fault-tolPi-ant system design. Fault detection and diagnosis involves creating a realistic model of the process, and using this model to analyse for fault conditions. The fault detection principles include feature extraction and pattern recognition, and analogue value limits and rate cf change limits. Fault recovery scheme? cover the realisation of redundancy ana back-up sub-systems, and state restoration techniques in the form of complete shutdowns, backward and forward recovery to a safe operating state. System design concepts include for the development of process control systems towards *hierarchical, level based distribution of functions. The level-based discussion is used as the basis for effective fault tolerant system design. Two case studies are included to show how fault recovery schemes were effected in a single process computer and in a distributed control system. Abstract