In order to be able to think clearly about any subject we need precise definitions of its basic terminology and concepts. If one reads the literature describing fault tolerant computing there is less agreement on fundamental models, concepts and terminology that would perhaps be expected. There are well established usages in particular subcommunities and many other individual workers take care to use terms carefully. Unfortunately there are also many papers in which terms are freely applied to concepts in an arbitrary and inconsistent way. This thesis attempts to bring together some of the concepts of fault tolerant computing and place them in a formal framework. The approach taken is to develop formal models of system structure and behaviour, and to define the basic concepts and terminology in terms of those models. The model of system structure is based on directed graphs and the model of behaviour is based on trace theory.

Report (M.S.)--Virginia Polytechnic Institute and State University. M.S. 1991. / Vita. Abstract. Includes bibliographical references (leaves 93-94). Also available via the Internet.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 90-96). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph. D.)--University of Wisconsin--Madison, 1981. / Typescript. Vita. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 190-194).

Thesis (Ph. D.)--University of Texas at Austin, 2006. / Vita. Includes bibliographical references.

No description available.

With the ever growing complexity of computer-controlled systems, the need for discrete- event systems has emerged. Many contributions have been done to improve and dis- cuss discrete-event system properties. In this thesis, we investigate the problem of fault tolerance in timed discrete-event systems. Our goal is to establish a timed fault tolerant supervisory control approach. We start by presenting our settings and providing different fault scenarios. We then provide four fault tolerant definitions to verify that the system will remain controllable in each scenario. Also, we introduce algorithms to verify timed controllability for each scenario. We implement a tool extension for the software research tool, DESpot, to verify timed controllability. Furthermore, we implement a tool extension to verify fault tolerant untimed controllability and nonblocking, and timed fault tolerant controllability for the fault scenarios. Finally, we present a simple example to illustrate our approach. / Thesis / Master of Applied Science (MASc)

In the recent past, there has been an increasing demand for low-cost safety critical applications. Custom-off-the-shelf (COTS) processors are preferred for usage in these applications due to their low cost. The reliability provided by these processors, however, is not sufficient to meet the safety requirements of these applications. Furthermore, due to the trends followed by the processor industry to enhance the performance of processors, the reliability provided by these processors is projected to decrease in the future. Traditional techniques for enhancing the reliability of computer systems are not viable for these applications due to the high overheads (and hence cost) incurred by them. This thesis describes fault tolerance techniques tailored for these applications, adhering to the tight overhead constraints in the area, memory, and performance dimensions. Techniques at both the hardware level (to be used by the processor manufacturers) and the software level (to be used by the application developers) are presented. At the hardware level, this thesis presents a technique for detecting faults in the processor control logic, for which techniques proposed previously incur very high overheads. Rather than detect all modeled faults, the technique protects against a subset of faults such that the best possible overall protection is achieved while incurring only permissible overheads. This subset of faults is selected depending on the probability of each individual fault causing damage to the architectural state of the processor and the overhead incurred in protecting against the fault. The technique is validated on control logic modules of an industrial processor. At the software level, this thesis concentrates on a category of errors called control flow errors. We describe an error detection technique which incurs lower overheads than any of the previously proposed techniques while at the same time detecting more errors than all of them. Even these low overheads may be too restrictive for some applications. For such applications, we present a technique for providing the best error detection capability possible at the overheads allowed. Once an error is detected, error recovery actions need to be performed. In this thesis, we present an error correction technique which automatically performs error recovery with a very low latency. The technique reuses the information available from the error detection technique to perform the recovery and hence, does not incur any additional performance penalty. All the techniques proposed at the software level have been integrated with GCC, a commonly used software compiler. This permits the fault tolerance to be incorporated into the application automatically as part of the compilation process itself. Evaluations are performed on SPEC and MiBench benchmark programs using an in-house software error injection framework. / text

published_or_final_version / Computer Science and Information Systems / Doctoral / Doctor of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy