A thesis submitted to the Faculty of Engineering, University of the Witwatersrand, Johannesburg, in fulfilment of the requirements for the degree of Doctor of Philosophy. / A new approach to the problem ofdesigning a control system for a run-of-mine (ROM) milling circuit is described. The ROM mill control problem is formalized in terms or a general linear system synthesis and analysis framework. Using this framework, u-synthesis and analysis is applied to a model of an industrial ROM milling circuit. The milling circuit uncertainty structure is obtained from plant perturbation tests. Correlations of plant parameter uncertainties and the choice of the location of uncertainty weights within the plant transfer function matrix structure, are discussed. Some comments are made as to possible sources of the plant uncertainties, and practical measures that can be taken to minimize them. The choice of performance weighting functions is discussed with regard to the economic and process-related importance of each plant output and issues of implementation such as the sampling rate to be used. A u-controller is obtained which provides robust performance in the face of significant model uncertainties. This controller is tested on a real industrial ROM milling circuit It is shown that the u-controller could be made to work on an industrial plant. Practical problems encountered are discussed, and reasons are given as to why the behaviour of the physical system differs form that observed in computer simulations. (Abbreviation abstract) / AC 2018

Chen Zhiyong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 54-57). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.ii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Nonlinear Control --- p.1 / Chapter 1.2 --- Global Stabilization --- p.2 / Chapter 1.3 --- Output Regulation --- p.3 / Chapter 1.4 --- Contributions of the Thesis --- p.4 / Chapter 2 --- Global Robust Stabilization of Cascaded Polynomial Systems --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Preliminaries --- p.6 / Chapter 2.3 --- Basic Results --- p.8 / Chapter 2.4 --- The Algorithm --- p.11 / Chapter 2.5 --- An Example --- p.14 / Chapter 2.6 --- Concluding Remarks --- p.16 / Chapter 3 --- Output Regulation of Singular Nonlinear Systems by Normal Output Feedback --- p.18 / Chapter 3.1 --- Introduction --- p.18 / Chapter 3.2 --- Preliminaries --- p.20 / Chapter 3.3 --- Main Result --- p.24 / Chapter 3.4 --- An Example --- p.34 / Chapter 3.5 --- Concluding Remarks --- p.35 / Chapter 4 --- Robust Output Regulation of Singular Nonlinear Systems --- p.37 / Chapter 4.1 --- Introduction --- p.37 / Chapter 4.2 --- Problem Description and Standard Assumptions --- p.38 / Chapter 4.3 --- A Preliminary Result --- p.40 / Chapter 4.4 --- Solvability of the Problem --- p.48 / Chapter 4.5 --- Concluding Remarks --- p.51 / Chapter 5 --- Conclusions --- p.52 / Bibliography --- p.54 / Biography --- p.58

Decision Feedback Equalization (DFE) in a data recovery channel filters the bit decision in the current symbol period in generating the sample at the comparator in the subsequent clock period. The operations of sampling, comparing, filtering the decision bits into a feedback signal, and subtraction of that feedback signal are cascaded, thereby establishing the critical timing path. Thus, this system, though simple, requires its components to have large bandwidths in order to achieve the high-speed response necessary to perform the described feedback function. For the entire system to run at speeds comparable to those of competing technologies (100MHz to 250MHz), the components must have bandwidths greater than 100MHz, and work together to provide a loop bandwidth of at least 100MHz. A 300MHz latching comparator and a 125MHz 6-bit current-DAC were designed in a 5V, 1 um CMOS n-well process for use in a DFE loop. Both blocks are fully differential and achieve an accuracy of 1/2 LSB (10uA) over a differential signal range of 1.28mA. This is true for their operations at speed, in isolated simulation and as contiguous blocks. The DAC power consumption is relatively high at 23mW, due to internal switching circuits which require a static current, but the comparator's power consumption is minimal at 5mW. / Graduation date: 1997

Thesis (M.S.)--University of Wisconsin--Madison, 1981. / Typescript. Title from title screen (viewed Mar. 27, 2007). Includes bibliographical references (leaves 66-68). Online version of the print original.

Thesis (Ph. D.)--University of Washington, 2001. / Vita. Includes bibliographical references (leaves 131-139).

Thesis--Ph. D., University of Hong Kong. / Mimeographed.

Thesis (Ph. D.)--West Virginia University, 2003. / Title from document title page. Document formatted into pages; contains xii, 156 p. : ill. (some col.) + MPEG video files. Includes MPEG video files. Includes abstract. Includes bibliographical references.

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published_or_final_version / Electrical Engineering / Doctoral / Doctor of Philosophy

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