A feed forward architecture is suggested that increases the complexity of conventional neural network components through the implementation of a more complex scheme of interconnection. This is done with a view to increasing the range of application of the feed forward paradigm. The uniqueness of this new network design is illustrated by developing an extended taxonomy of accepted published constructs specific and similar to the higher order, product kernel approximations achievable using "parallel paths". Network topologies from this taxonomy are then compared to each other and the architectures containing parallel paths. In attempting this comparison, the context of the term "network topology" is reconsidered. The output of "channels" in these parallel paths are the products of a conventional connection as observed facilitating interconnection between two layers in a multilayered perceptron and the output of a network processing unit, a "control element", that can assume the identity of a number of pre-existing processing paradigms. The inherent property of universal approximation is tested by existence proof and the method found to be inconclusive. In so doing an argument is suggested to indicate that the parametric nature of the functions as determined by conditions upon initialization may only lead to conditional approximations. The property of universal approximation is neither, confirmed or denied. Universal approximation cannot be conclusively determined by the application of Stone Weierstrass Theorem, as adopted from real analysis. This novel implementation requires modifications to component concepts and the training algorithm. The inspiration for these modifications is related back to previously published work that also provides the basis of "proof of concept". By achieving proof of concept the appropriateness of considering network topology without assessing the impact of the method of training on this topology is considered and discussed in some detail. Results of limited testing are discussed with an emphasis on visualising component contributions to the global network output.

In this dissertation, the combined optical link, where the baseband digital signal and wireless signal are transmitted simultaneously over a multi-mode fiber (MMF) using an VCSEL and received through a photoreceiver and a feed forward equalizer (FFE). For this hybrid optical link, a new type of combiner is developed using the multi-layer organic (MLO) process. For the overall link simulation, a rate-equation-based VCSEL model is developed with circuit components. This model describes the high-speed modulation characteristic as well as the thermal effect on the L-I (light vs. bias current) characteristic. Additionally, The FFE is developed to further extend a MMF distance by compensating differential modal delay (DMD) in MMF. Two different implementation approaches are taken for the FFE by passive LC ladder based delay line and active inductance peaking delay line structure. To overcome the voltage headroom limitation of the conventional Gilbert cell architecture, modified Gilbert cell is presented and implemented as a multiplier cell for both FFEs. The FFEs are fully integrated on a single chip and fabricated by a standard 0.18 ?m CMOS process. The developed FFE successfully rebuild the distorted signal form the MMF at 10 Gbps data rate.

Being able to read at a fluent rate has many advantages to the individual in both educational and wider social contexts throughout life. To be a fluent reader means that the individual can sustain high accuracy while reading at a rate appropriate to the material and the setting, and implies the development of automaticity in the cognitive processes involved in reading. Fluency has not, however, been the focus of much research. In this study an observational learning technique - feedforward video self modelling (FFVSM) - was used to improve children’s reading fluency. Eleven primary school children aged between 72 and 108 months, 4 girls and 7 boys, viewed edited video footage of themselves seemingly reading a difficult text at a fluent rate six times over a two week period. The results showed that the majority of the children improved their reading fluency, comprehension and accuracy, as well as their reader self-perception (a proxy measure of self-efficacy). These positive results suggest that FFVSM could be a rapid, cost effective intervention to be used within educational settings to promote fluent reading.

Thesis (Ph. D.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 156-160). Also available via the Internet.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2006. / Includes bibliographical references. Also available in electronic version.

With the rise of the Internet of Things, more and more devices are being connected to the internet, driving up the demand for wireless connectivity. In addition to advancing the current RF technology, optical communication, specifically IR wireless communication, is a competitive option to help offload some of the wireless demand. However, one of the crucial components for an effective IR system is the ability to quickly and controllably steer the IR light around a room, providing data as a device moves. This thesis focuses on tip-tilt MEMS micromirrors for indoor optical wireless communication (OWC), specifically two key aspects, (1) design and (2) controls. We discuss two unique tip-tilt mirror designs for indoor OWC. The first is an electrothermal varifocal mirror capable of changing its shape, and therefore the shape of the beam in real time. The mirror's radius of curvature can range between -0.48 mm and 20.5 mm, focusing light from a bare fiber from a half-angle divergence of 5° to 0.18° The second mirror uses electromagnetic actuation to achieve a large quasi-static angular range capable of ±60° mechanical ±120° optical) about two rotation axes. In other words, with a laser beam focused on the mirror from the zenith, the device could direct the beam anywhere in a hemisphere. In addition to the device design, we discuss a series of control techniques that can improve the step-and-settle response time of a MEMS device by orders of magnitude compared to a traditional step input. For example, this technique is used to settle the above magnet mirror within 4.5 ms, a factor of 300 improvement over the 1.35 s settling time of a traditional step input. These techniques can be used in conjunction with pulse width modulation (PWM) to provide a fast, low-cost controls solution with no loss in performance. Designing mirrors with these types of controls in mind will not only benefit OWC but enable new applications as well.

This dissertation deals with the problem of analyzing feed-forward priority queueing systems. In this type of system incoming units enter one of n priority queues if the service facility is busy. Units in the highest priority queue are served on a first-come-first-served basis while units in the lower priority queues will only be serviced if there are no higher priority units. A predefined delay time is employed for each queue so that a unit waiting in a lower priority queue is able to transfer to the next higher queue. The waiting unit will transfer to a higher priority queue if its waiting time becomes equal to the predefined delay time. Otherwise, the unit enters the service facility. Units receive service until completion, and at that time, leave the queueing system. The initial approach in this dissertation to analyze such a system is to develop the steady state mathematical expressions for a feed-forward system with two priority queues (FF₂). This represents the simplest case for feed-forward queueing systems (FF_n), and development of the mathematical expressions for this model indicates the tractability of higher order models. Numerical results are obtained from the FF₂ mathematical model by defining input parameters for the delay process, interarrival distribution, and service distribution. To aid in validating the cumulative waiting time results, W_m(t), produced by the mathematical model, an FF₂ simulation model is developed. Results from the two procedures compare favorably which aids in substantiating the notion that the FF₂ model is correct as well as the notion that the simulation model is operating properly. As is often the case, when systems become too complex to be analyzed mathematically, simulation is warranted. Such is the case in this research. Thus, a general simulation model is developed for analyzing higher order systems. This model is capable of representing any FF_n queueing system by simple manipulation. A modified Runge-Kutta procedure is developed for an FF₇ system to ascertain the behavior of the system under transient conditions. Transient results are also obtained from the simulation model. A comparison of the results from the Runge-Kutta and simulation procedures indicate that they agree quite favorably. This agreement aids in substantiating that both methods are properly formulated. The major goal of this research, to develop a model for analyzing FF_n queueing systems, has been accomplished. Various mathematical expressions for analyzing FF₂ systems have been developed. Because higher order models are mathematically intractable, a general simulation model has been developed and substantiated for both steady state and transient conditions. A modified Runge-Kutta procedure has also been developed to aid in analyzing the transient case. / Ph. D.

No description available.

Call number: LD2668 .T4 1986 B34 / Master of Science

<p>Sigma-delta modulators (SDM) have come up as an attractive candidatefor analog-to-digital conversion in single chip front ends thanks to the continuousimproving performance. The major disadvantage is the limited bandwidthdue to the need of oversampling. Therefore, extending these convertersto broadband applications requires lowering the oversampling ratio (OSR) inorder. The aim of this thesis is the investigation on the topology and structureof sigma-delta modulators suitable for wideband applications, e.g. wireline orwireless communication system applications having a digital baseband aboutone to ten MHz.It has recently become very popular to feedforward the input signal inwideband sigma-delta modulators, so that the integrators only process quantizationerrors. The advantage being that the actual signal is not distorted byopamp and integrator nonlinearities. An improved feedforward 2-2 cascadedstructure is presented based on unity-gain signal transfer function (STF). Theimproved signal-to-noise-ratio (SNR) is obtained by optimizing zero placementof the noise transfer function (NTF) and adopting multi-bit quantizer.The proposed structure has low distortion across the entire input range.In high order single loop continuous-time (CT) sigma-delta modulator, excessloop delay may cause instability. Previous techniques in compensation ofinternal quantizer and feedback DAC delay are studied especially for the feedforwardstructure. Two alternative low power feedforward continuous-timesigma-delta modulators with excess loop delay compensation are proposed.Simulation based CT modulator synthesis from discrete time topologies isadopted to obtain the loop filter coefficients. Design examples are given toillustrate the proposed structure and synthesis methodology.Continuous time quadrature bandpass sigma-delta modulators (QBSDM)efficiently realize asymmetric noise-shaping due to its complex filtering embeddedin the loops. The effect of different feedback waveforms inside themodulator on the NTF of quadrature sigma-delta modulators is presented.An observation is made that a complex NTF can be realized by implementingthe loop as a cascade of complex integrators with a SCR feedback digital-toanalogconverter (DAC), which is desirable for its lower sensitivity to loopmismatch. The QBSDM design for different bandpass center frequencies relativeto the sampling frequency is illustrated.The last part of the thesis is devoted to the design of a wideband reconfigurablesigma-delta pipelined modulator, which consists of a 2-1-1 cascadedmodulator and a pipelined analog-to-digital convertor (ADC) as a multi-bitquantizer in the last stage. It is scalable for different bandwidth/resolutionapplication. The detail design is presented from system to circuit level. Theprototype chip is fabricated in TSMC 0.25um process and measured on thetest bench. The measurement results show that a SNR over 60dB is obtainedwith a sampling frequency of 70 MHz and an OSR of ten.</p>