The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications. / Master of Science / Everyone today is dependent on some sort of an electronic device be it a computer, laptop, tablet or a phone powered by the boom of the Silicon Valley. All of which have witnessed significant improvement in performance due to the increase in the number of transistors in a microprocessor (similar to horsepower of a car) which is made possible due to the dimensional scaling of the transistor device features (currently at 14nm). With increased transistor density, a higher power consumption is consequential creating a trade-off between performance and power consumption (battery life). However, there are limitations as to how small a transistor can be scaled. This has provided precedence to employ alternate materials such as III-V alloys and Germanium to reduce power consumption (due to a lower band gap; which dictates how much energy is consumed) while simultaneously improving device performance by providing a mobility boost (which is a property of the aforementioned materials that allows current to flow faster, thereby improving device performance). The aim of this work is evaluate leading device architectures incorporating alternate channel materials (InGaAs in particular which is a very suitable III-V alloy) to develop a simulation model that is calibrated to existing data to project device performance future transistor nodes.

Aggressive scaling required to augment device performance has caused conventional electrode materials to approach their physical scaling limits. Alternative metal gate/high dielectric constant (MG/High-[kappa]) stacks have been implemented successfully in commercial devices and hold promise for further scaling based performance advances. Existing MG/High-[kappa] technology does not achieve a single metal n-MOS to p-MOS effective work function (EWF) tuning range suitable for bulk silicon (Si) device applications. Dual metal gates (DMGs) utilizing a separate metal for n-MOS and p-MOS electrodes increases the cost and complexity of fabrication. The research presented herein introduces a method by which the cost and complexity of MG/High-[kappa] device fabrication may be reduced. Innovative fin field effect transistors (FinFETs) incorporating 3 dimensional ultra thin body silicon on oxide (3-D UTB-SOI) technology display superior electrical characteristics compared to bulk Si devices at the nanometer (nm) dimension and require only a +/-200meV n-MOS to p-MOS EWF tuning range around the Si mid-gap. Single metals capable of achieving this +/-200meV EWF tuning range have been evaluated herein and the tuning mechanisms investigated and engineered to develop a single MG/High-[kappa] FinFET the fabrication complexity of which is reduced by 40%. More specifically, the research shows that the metal thickness of titanium nitride/hafnium silicon oxide (TiN/HfSiOx) gate stack may be engineered to achieve an n-MOS (thinner TiN) to p-MOS (thicker TiN) appropriate FinFET EWF tuning range. FinFETs may be fabricated by depositing a single p-MOS appropriate TiN thickness which may be selectively etched back to achieve thinner, n-MOS appropriate films. Similar electrical behavior is exhibited by etched back and as deposited TiN electrode FinFETs. The single metal etch back fabrication method removes many of the additional steps required for DMG fabrication and preserves the integrity of the MG/High-[kappa] interface between n-MOS and p-MOS devices. These advantages result in reduced fabrication complexity and improved reliability and reproducibility. / text