It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature size shrinking to about 10nm, off-chip interconnects in an area array format will require a pitch of 95 µm. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, as part of this research a unique parallel-path approach has been developed which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It also provides for redundancy and thus results in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, as part of this research a variable compliance approach has been developed so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work has developed a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigated key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches are demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed in this research are generic in nature and can be extended to other aspects of electronic packaging.

La technologie flip chip est de plus en plus répandue dans l'industrie électronique [trois dimensions (3D) System in Package] et est principalement utilisée pour la fabrication de réseaux détecteurs de grand format (mégapixels) et faible pas. Pour étudier la fiabilité de ces assemblages, des simulations numériques basées sur des méthodes d'éléments finis semblent être l'approche la moins chère. Cependant, de très grands assemblages contiennent plus d'un million de billes de brasure, et le processus d'optimisation de ces structures par des simulations numériques se révèle être une tâche très fastidieuse. Dans de nombreuses applications, la couche d'interconnexion de tels assemblages flip chip se compose de microbilles de brasure noyées dans de l'époxy. Pour ces configurations, nous proposons une approche alternative, qui consiste à remplacer cette couche d'interconnexion hétérogène par un matériau homogène équivalent (MHE). Un modèle micromécanique pour l'estimation de ses propriétés thermoélastiques équivalentes a été mis au point. La loi de comportement obtenue pour le MHE a ensuite été implémentée dans le logiciel par éléments finis (Abaqus®). Les propriétés élastiques des matériaux de l'assemblage sont définies par la littérature et également déterminées expérimentalement par une méthode de caractérisation mécanique : la nano-indentation. Les réponses thermomécaniques des assemblages testés soumis à des chargements correspondant aux conditions de fabrication ont été analysées. La technique d'homogénéisation-localisation a permis d'estimer les valeurs moyennes des contraintes et des déformations dans chaque phase de la couche d'interconnexion. Pour accéder plus précisément aux champs de contraintes et déformations dans ces phases, deux modèles de zoom structurel (couplage de modèles et submodeling), en tenant compte de la géométrie réelle de la bille de brasure, ont été testés. Les champs de contrainte et de déformation locaux obtenus corroborent avec les initiations de dommage observées expérimentalement sur les billes de brasure / Flip chip technology is increasingly prevalent in electronics assembly [threedimensional (3D) system in package] and is mainly used at fine pitch for manufacture of megapixel large focal-plane detector arrays. To estimate the reliability of these assemblies, numerical simulations based on finite-element methods appear to be the cheapest approach. However, very large assemblies contain more than one million solder bumps, and the optimization process of such structures through numerical simulations turns out to be a very time-consuming task. In many applications, the interconnection layer of such flip-chip assemblies consists of solder bumps embedded in epoxy filler. For such configurations, we propose an alternative approach, which consists in replacing this heterogeneous interconnection layer by a homogeneous equivalent material (HEM). A micromechanical model for the estimation of its equivalent thermoelastic properties has been developed. The constitutive law of the HEM obtained was then implemented in finite-element software (Abaqus®). Elastic properties of materials that compose the assembly were found in literature and by using mechanical characterization method especially nano-indentation. Thermomechanical responses of tested assemblies submitted to loads corresponding to manufacturing conditions have been analyzed. The homogenization-localization process allowed estimation of the mean values of stresses and strains in each phase of the interconnection layer. To access more precisely to the stress and strain fields in these phases, two models of structural zoom (model coupling and submodeling), taking into account the real solder bump geometry, have been tested. The local stress and strain fields obtained corroborate the experimentally damage initiation of the solder bumps observed