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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Sintetizador analógico de sinais ortogonais: projeto e construção usando tecnologia CMOS

Oliveira, Vlademir de Jesus Silva [UNESP] 30 March 2004 (has links) (PDF)
Made available in DSpace on 2014-06-11T19:24:46Z (GMT). No. of bitstreams: 0 Previous issue date: 2004-03-30Bitstream added on 2014-06-13T18:21:14Z : No. of bitstreams: 1 oliveira_vjs_me_ilha.pdf: 825294 bytes, checksum: 1231181cf2748d4fec35e435930c317b (MD5) / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Nesse trabalho, propõe-se o projeto e implementação de um sintetizador de sinais ortogonais utilizando técnicas de circuito integrado e processo CMOS. O circuito do sintetizador baseia-se em um modelo matemático que utiliza multiplicadores e integradores analógicos, para geração de bases de funções ortogonais, tais como os polinômios de Legendre, as funções de base coseno e seno, a smoothed-cosine basis e os polinômios de Hermite. Funções ortogonais são bastante empregadas em processamento de sinais, e a implementação deste método matemático é capaz de gerar vários tipos de funções em um mesmo circuito integrado. O projeto proposto utiliza blocos analógicos funcionais para implementar o sintetizador. Os blocos que compõem o sintetizador foram projetados utilizando circuitos diferenciais, processamento em modo de corrente e técnicas de low-voltage. Algumas topologias utilizadas estão descritas na literatura, sendo que algumas foram adaptadas e mesmo modificadas, como no caso do multiplicador de corrente. Outras tiveram que ser propostas. As simulações e os resultados experimentais mostraram que o sintetizador é capaz de gerar funções ortogonais com amplitude e distorções satisfatórias. O sintetizador pode ser alimentado em 3V, tal qual foi projetado, tem faixa de entrada de ±20 μA e apresenta DHT (distorção harmônica total) inferior a 4% no quinto e último estágio em cascata. / In this work, a design and implementation of a synthesizer of orthogonal signals using CMOS technology and design technique for integrated circuits is proposed. The synthesizer circuit used analog multipliers and integrators for produce orthogonal functions such as Legendre polynomials, cosine and sine basis of functions, smoothed-cosine basis and Hermite polynomials. Orthogonal functions can be employed in signal processing and the implementation proposed can generate several kinds of functions in the same integrated circuit. In the synthesizer design building blocks was employed. The synthesizer’s blocks were design using differential circuits, low-voltage and current-mode techniques. Some topologies from papers were adapted or modified, as in the case of the current multiplier. Other topologies had to be proposed. The simulation and experimental results have shown that the synthesizer is able to produce orthogonal functions with satisfactory quality in distortions and amplitude. The synthesizer has a 3V supply voltage, a input current range of ±20 μA and it presents less than 4% of THD (Total Harmonic Distortion) in the last output in cascade.
2

Sintetizador analógico de sinais ortogonais : projeto e construção usando tecnologia CMOS /

Oliveira, Vlademir de Jesus Silva. January 2004 (has links)
Orientador: Nobuo Oki / Banca: Saulo Finco / Banca: Cláudio Kitano / Resumo: Nesse trabalho, propõe-se o projeto e implementação de um sintetizador de sinais ortogonais utilizando técnicas de circuito integrado e processo CMOS. O circuito do sintetizador baseia-se em um modelo matemático que utiliza multiplicadores e integradores analógicos, para geração de bases de funções ortogonais, tais como os polinômios de Legendre, as funções de base coseno e seno, a smoothed-cosine basis e os polinômios de Hermite. Funções ortogonais são bastante empregadas em processamento de sinais, e a implementação deste método matemático é capaz de gerar vários tipos de funções em um mesmo circuito integrado. O projeto proposto utiliza blocos analógicos funcionais para implementar o sintetizador. Os blocos que compõem o sintetizador foram projetados utilizando circuitos diferenciais, processamento em modo de corrente e técnicas de low-voltage. Algumas topologias utilizadas estão descritas na literatura, sendo que algumas foram adaptadas e mesmo modificadas, como no caso do multiplicador de corrente. Outras tiveram que ser propostas. As simulações e os resultados experimentais mostraram que o sintetizador é capaz de gerar funções ortogonais com amplitude e distorções satisfatórias. O sintetizador pode ser alimentado em 3V, tal qual foi projetado, tem faixa de entrada de ±20 μA e apresenta DHT (distorção harmônica total) inferior a 4% no quinto e último estágio em cascata. / Abstract: In this work, a design and implementation of a synthesizer of orthogonal signals using CMOS technology and design technique for integrated circuits is proposed. The synthesizer circuit used analog multipliers and integrators for produce orthogonal functions such as Legendre polynomials, cosine and sine basis of functions, smoothed-cosine basis and Hermite polynomials. Orthogonal functions can be employed in signal processing and the implementation proposed can generate several kinds of functions in the same integrated circuit. In the synthesizer design building blocks was employed. The synthesizer's blocks were design using differential circuits, low-voltage and current-mode techniques. Some topologies from papers were adapted or modified, as in the case of the current multiplier. Other topologies had to be proposed. The simulation and experimental results have shown that the synthesizer is able to produce orthogonal functions with satisfactory quality in distortions and amplitude. The synthesizer has a 3V supply voltage, a input current range of ±20 μA and it presents less than 4% of THD (Total Harmonic Distortion) in the last output in cascade. / Mestre
3

Σχεδίαση αναλογικών ολοκληρωμένων φίλτρων χαμηλής τάσης τροφοδοσίας στο πεδίο του υπερβολικού ημιτόνου

Κασίμης, Χρυσόστομος 07 June 2013 (has links)
Η παρούσα διδακτορική διατριβή εστίασε το ενδιαφέρον της στην διερεύνηση των αναλογικών ολοκληρωμένων φίλτρων της κατηγορίας ELIN εξωτερικά γραμμικά, εσωτερικά μη-γραμμικά. Συγκεκριμένα μελετήθηκαν και σχεδιάστηκαν, νέες δομές φίλτρων συμπίεσης-αποσυμπίεσης του προς επεξεργασία σήματος στο πεδίο του υπερβολικού ημιτόνου χαμηλής τάσης τροφοδοσίας. Η γοργή ανάπτυξη της μικροηλεκτρονικής στην υλοποίηση συστημάτων υψηλής αξιοπιστίας και απόδοσης μικρού βάρους και όγκου όπως φορητών ηλεκτρονικών πολυμέσων, επικοινωνιών, βιοϊατρικών συσκευών, ωθεί στην σχεδίαση των ολοκληρωμένων κυκλωμάτων που τα απαρτίζουν με μειωμένη κατανάλωση ισχύος και κατ’ επέκταση χαμηλής τάσης τροφοδοσίας. Σ’ ένα ολοκληρωμένο κύκλωμα η ενσωμάτωση αναλογικών και ψηφιακών κυκλωμάτων σε περιβάλλον χαμηλής τάσης τροφοδοσίας, ώστε το κόστος των διατάξεων να διατηρείται χαμηλό, επηρεάζει άμεσα την απόδοση του αναλογικού τμήματος, προτάσσοντας την ανάγκη για νέες αρχιτεκτονικές σχεδίασης του. Οι διατάξεις των αναλογικών φίλτρων αποτελούν συχνά δομικό στοιχείο των ολοκληρωμένων κυκλωμάτων και η διερεύνηση τους για την επίτευξη μεγάλης δυναμικής περιοχής, ηλεκτρονική ρύθμισης της απόκρισης συχνότητας και ταυτόχρονα χαμηλής κατανάλωσης ισχύος, έχει απασχολήσει αρκετά το ενδιαφέρον της ερευνητικής κοινότητας. Προτείνεται αρχικά η συστηματική σχεδίαση φίλτρων υψηλής τάξης στο πεδίο του υπερβολικού ημιτόνου, αποσκοπώντας στη βελτίωση της διαδικασίας υλοποίησης τους, με χρήση ήδη υπαρχουσών μη-γραμμικών διαγωγών υπερβολικού ημιτόνου, συνημίτονου. Η συμπίεση-αποσυμπίεση του προς επεξεργασία σήματος επιτυγχάνεται με την κατάλληλη τοποθέτηση συμπληρωματικών τελεστών ενώ ταυτόχρονα διατηρείται γραμμική η συνολική συμπεριφορά των διατάξεων. Με γνώμονα την εφαρμογή τους σε βιοϊατρικές συσκευές, εξομοιώνεται με δύο διαφορετικούς τρόπους φίλτρο 3ης τάξης leapfrog με συχνότητα αποκοπής 10Hz και τα αποτελέσματα που προκύπτουν συγκρίνονται με αντίστοιχο γραμμικής συμπεριφοράς. Στην συνέχεια, υλοποιείται η σχεδίαση BiCMOS φίλτρων οποιασδήποτε τάξης, δομημένα από μη-γραμμικούς διαγωγούς υπερβολικού ημιτόνου με δυνατότητα λειτουργίας σε υψηλές συχνότητες και σε χαμηλή τάση τροφοδοσίας. Επιλέγονται οι μέθοδοι του γραμμικού μετασχηματισμού, λειτουργικής και τοπολογικής εξομοίωσης ενός πρωτότυπου ελλειπτικού βαθυπερατού 3ης τάξης με συχνότητα αποκοπής 0.5 kHz και κυμάτωση στην ζώνη διέλευσης 0.5dB. Ακολουθεί ανάλυση και σύγκριση των αποτελεσμάτων που προκύπτουν στο περιβάλλον Analog Virtuoso της Cadence Software, της τεχνολογίας AMS CMOS S35 0.35μm, μεταξύ των φίλτρων στο πεδίο του υπερβολικού ημιτόνου καθώς και με αντίστοιχες διατάξεις στο πεδίο του λογαρίθμου τάξης-ΑΒ και (OTA)-C στο γραμμικό χώρο. Προτείνεται ακόμη, η BiCMOS σχεδίαση γενικευμένων φίλτρων 2ης τάξης απλής εισόδου-πολλαπλών εξόδων και πολλαπλής εισόδου-απλής εξόδου, με δυνατότητα λειτουργίας σε περιβάλλον χαμηλής τάσης τροφοδοσίας, ηλεκτρονικής ρύθμισης της συχνότητας αποκοπής ω0 του συντελεστή ποιότητας Q και της ορθογώνιας μεταβολής μεταξύ των. Από την εξομοίωση τους πρόκυψε ότι είναι ενεργειακά αποδοτικότερη η υλοποίηση τους συγκρινόμενα με αντίστοιχα στο πεδίο του λογαρίθμου. Τέλος, στα πλαίσια υλοποίησης βιοϊατρικών εφαρμογών προτείνεται η σχεδίαση ενός μη-γραμμικού τελεστή ενέργειας στο πεδίο του υπερβολικού ημιτόνου για την ανίχνευση αιχμών δραστηριότητας σε νευρωνικά δίκτυα με τάση τροφοδοσίας 0.5V. Ο μη-γραμμικός διαγωγός υπερβολικού ημιτόνου, του οποίου ο διαγραμμικός βρόγχος αποτελείται από (pMOS) τρανζίστορ δομεί τους διαφοριστές και πολλαπλασιαστές τεσσάρων τεταρτημορίων τάξης-ΑΒ που απαρτίζουν την διάταξη. Εξομοιώνεται, κάνοντας χρήση CMOS τρανζίστορ της τεχνολογίας TSMC 130 nm, στο περιβάλλον Analog Virtuoso της Cadence Software και συγκρινόμενος με ήδη υπάρχουσες διατάξεις, παρουσιάζει την μικρότερη κατανάλωση ισχύος. / This present Ph.D dissertation is focused its interest on the design of low voltage analog integrated circuits. Companding (compressing-expanding) systems are Externally Linear, Internally Non-linear (ELIN) processors with potential for low-voltage operation capability. In this direction novel topologies of companding filters in the Sinh-Domain are introduced. Τhe radical technological developments of microelectronics in the systems implementation with high reliability and performance, such as portable electronic devices for multimedia, communications and biomedical systems, demand the design of integrated circuits with reduced power consumption and thus low voltage supply. Integration of analog and digital circuits of systems-on-chip – (SoC) in order to be kept the low cost, directly affects the performance of the analog section, pointing forward the need for novel architectural design. One of the basic building blocks for circuit design is analog filters and their investigation in order to achieved large dynamic range, electronic tuning capability of their frequency characteristics which has gained a significant research effort toward these goals. At first, a new systematic method for designing Sinh-Domain filters is introduced. The proposed method offers the benefits of facilitating the design procedure of high-order Sinh-Domain filters using already introduced building blocks and of the absence of any restriction concerning the type and/or the order of the realized filter function. This is achieved by employing an appropriate set of complementary operators, in order to transpose the conventional functional block diagram representation of each linear operation to the corresponding one into the Sinh-Domain. In order to demonstrate the validity of the proposed systematic method, 3rd order leapfrog low-pass filter with a cut-off frequency at 10Hz which is typical for biomedical applications, has been realized following two alternative approaches and, also, a comparison has been performed among them and a conventional linear filter where the most important performance factors have been taken into account. Continuing, novel BiCMOS sinh-domain filter topologies, derived according to operational emulation, component substitution techniques and Linear Transformation of the corresponding 3rd-order passive prototype filters, with a cut-off frequency at 0.5 kHz and pass-band ripple 0.5dB, is proposed. This has been achieved by utilizing BiCMOS nonlinear ransconductor cells into the sinh domain. An attractive benefit of the proposed filter topologies is their capability for operating in high frequencies and a low-voltage environment. The performance of a leapfrog sinh-domain filter has been compared, using the Analog Design Environment of the Cadence software using AMS CMOS S35 0.35μm, with those of the corresponding log-domain and operational ransconductance amplifier (OTA)-C filters. Furthermore, the design of a family of Sinh-Domain universal biquad filters are introduced offering the benefits of low-voltage operation and, simultaneously, power efficient realizations in comparison with the corresponding already proposed biquads. Also, they have the capability for orthogonal adjustment between the resonance frequency and Q factor of the filter and these parameters could be also electronically adjusted through appropriate dc currents. Thus, they could be considered as attractive blocks for realizing high-performance analog signal processing systems. Finally, a Sinh-Domain topology for realizing the Non Linear Energy Operator (NEO) is introduced. For this purpose, a novel Sinh-Domain differentiator is proposed which offers the benefits of ultra low-voltage operation capability and electronic tuning of the realized time-constant. The whole system is also constructed from a four-quadrant current multiplier, realized by employing appropriately configured non-linear transconductors. Considering a single power supply voltage of 0.5V, the behavior of the proposed Sinh-Domain NEO realization has been simulated using the Analog Design Environment of the Cadence software using TSMC 130 nm design hit.

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