12 September 2011
Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage ment technique, which aims to reduce the energy consumption of computing platforms by dynamically scaling the CPU frequency. Real-Time DVFS (RT-DVFS) is a branch of DVFS, which reduces CPU energy consumption through DVFS, while at the same time ensures that task time constraints are satisfied by constructing appropriate real-time task schedules. The literature presents numerous RT-DVFS scheduling algorithms, which employ different techniques to utilize the CPU idle time to scale the frequency. Many of these algorithms have been experimentally studied through simulations, but have not been implemented on real hardware platforms. Though simulation-based experimental studies can provide a first-order understanding, implementation-based studies can reveal actual timeliness and energy consumption behaviours. This is particularly important, when it is difficult to devise accurate simulation models of hardware, which is increasingly the case with modern systems. In this thesis, we study the timeliness and energy consumption behaviours of fourteen state- of-the-art RT-DVFS schedulers by implementing and evaluating them on two hardware platforms. The schedulers include CC-EDF, LA-EDF, REUA, DRA andd AGR1 among others, and the hardware platforms include ASUS laptop with the Intel I5 processor and a mother- board with the AMD Zacate processor. We implemented these schedulers in the ChronOS real-time Linux kernel and measured their actual timeliness and energy behaviours under a range of workloads including CPU-intensive, memory-intensive, mutual exclusion lock-intensive, and processor-underloaded and overloaded workloads. Our studies reveal that measuring the CPU power consumption as the cube of CPU frequency can lead to incorrect conclusions. In particular, it ignores the idle state CPU power consumption, which is orders of magnitude smaller than the active power consumption. Consequently, power savings obtained by exclusively optimizing active power consumption (i.e., RT-DVFS) may be offset by completing tasks sooner by running them at the highest frequency and transitioning to the idle state earlier (i.e., no DVFS). Thus, the active power consumption savings of the RT-DVFS techniques' that we report are orders of magnitude smaller than their simulation-based savings reported in the literature. / Master of Science
Maharaj, Bodhaswar Tikanath Jugpershad
29 July 2008
This thesis investigates multiple-input-multiple-output (MIMO) channel modelling for a wideband indoor environment. Initially the theoretical basis of geometric modelling for a typical indoor environment is looked at, and a space-time model is formulated. The transmit and receive antenna correlation is then separated and is expressed in terms of antenna element spacing, the scattering parameter, mean angle of arrival and number of antenna elements employed. These parameters are used to analyze their effect on the capacity for this environment. Then the wideband indoor channel operating at center frequencies of 2.4 GHz and 5.2 GHz is investigated. The concept of MIMO frequency scaling is introduced and applied to the data obtained in the measurement campaign undertaken at the University of Pretoria. Issues of frequency scaling of capacity, spatial correlation and the joint RX/TX double direction channel response for this indoor environment are investigated. The maximum entropy (ME) approach to MIMO channel modelling is investigated and a new basis is developed for the determination of the covariance matrix when only the RX/TX covariance is known. Finally, results comparing this model with the established Kronecker model and its application for the joint RX/TX spatial power spectra, using a beamformer, are evaluated. Conclusions are then drawn and future research opportunities are highlighted. / Thesis (PhD)--University of Pretoria, 2008. / Electrical, Electronic and Computer Engineering / unrestricted
Power-Performance-Predictability: Managing the Three Cornerstones of Resource Constrained Real-Time System DesignMukherjee, Anway 08 November 2019 (has links)
This dissertation explores several challenges that plague the hardware-software co-design of popular resource constrained real-time embedded systems. We specifically tackle existing real-world problems, and address them through our design solutions which are highly scalable, and have practical feasibility as verified through our solution implementation on real-world hardware. We address the problem of poor battery life in mobile embedded devices caused due to side-by-side execution of multiple applications in split-screen mode. Existing industry solutions either restricts the number of applications that can run simultaneously, limit their functionality, and/or increase the hardware capacity of the battery associated with the system. We exploit the gap in research on performance and power trade-off in smartphones to propose an integrated energy management solution, that judiciously minimizes the system-wide energy consumption with negligible effect on its quality of service (QoS). Another important real-world requirement in today's interconnected world is the need for security. In the domain of real-time computing, it is not only necessary to secure the system but also maintain its timeliness. Some example security mechanisms that may be used in a hard real-time system include, but are not limited to, security keys, protection of intellectual property (IP) of firmware and application software, one time password (OTP) for software certification on-the-fly, and authenticated computational off-loading. Existing design solutions require expensive, custom-built hardware with long time-to-market or time-to-deployment cycle. A readily available alternative is the use of trusted execution environment (TEE) on commercial off-the-shelf (COTS) embedded processors. However, utilizing TEE creates multiple challenges from a real-time perspective, which includes additional time overhead resulting in possible deadline misses. Second, trusted execution may adversely affect the deterministic execution of the system, as tasks running inside a TEE may need to communicate with other tasks that are executing on the native real-time operating system. We propose three different solutions to address the need for a new task model that can capture the complex relationship between performance and predictability for real-time tasks that require secure execution inside TEE. We also present novel task assignment and scheduling frameworks for real-time trusted execution on COTS processors to improve task set schedulability. We extensively assess the pros and cons of our proposed approaches in comparison to the state-of-the-art techniques in custom-built real-world hardware for feasibility, and simulated environments to test our solutions' scalability. / Doctor of Philosophy / Today's real-world problems demand real-time solutions. These solutions need to be practically feasible, and scale well with increasing end user demands. They also need to maintain a balance between system performance and predictability, while achieving minimum energy consumption. A recent example of technological design problem involves ways to improve the battery lifetime of mobile embedded devices, for example, smartphones, while still achieving the required performance objectives. For instance, smartphones that run Android OS has the capability to run multiple applications concurrently using a newly introduced split-screen mode of execution, where applications can run side-by-side at the same time on screen while using the same shared resources (e.g., CPU, memory bandwidth, peripheral devices etc.). While this can improve the overall performance of the system, it can also lead to increased energy consumption, thereby directly affecting the battery life. Another technological design problem involves ways to protect confidential proprietary information from being siphoned out of devices by external attackers. Let us consider a surveillance unmanned aerial vehicle (UAV) as an example. The UAV must perform sensitive tasks, such as obtaining coordinates of interest for surveillance, within a given time duration, also known as task deadline. However, an attacker may learn how the UAV communicates with ground control, and take control of the UAV, along with the sensitive information it carries. Therefore, it is crucial to protect such sensitive information from access by an unauthorized party, while maintaining the system's task deadlines. In this dissertation, we explore these two real-world design problems in depth, observe the challenges associated with them, while presenting several solutions to tackle the issues. We extensively assess the pros and cons of our proposed approaches in comparison to the state-of- the-art techniques in custom-built real-world hardware, and simulated environments to test our solutions' scalability.
Wamhoff, Jons-Tobias, Diestelhorst, Stephan, Fetzer, Christof, Marlier, Patrick, Felber, Pascal, Dice, Dave
26 November 2013
(has links) (PDF)
Several modern multi-core architectures support the dynamic control of the CPU's clock rate, allowing processor cores to temporarily operate at speeds exceeding the operational base frequency. Conversely, cores can operate at a lower speed or be disabled altogether to save power. Such facilities are notably provided by Intel's Turbo Boost and AMD's Turbo CORE technologies. Frequency control is typically driven by the operating system which requests changes to the performance state of the processor based on the current load of the system. In this paper, we investigate the use of dynamic frequency scaling from user space to speed up multi-threaded applications that must occasionally execute time-critical tasks or to solve problems that have heterogeneous computing requirements. We propose a general-purpose library that allows selective control of the frequency of the cores - subject to the limitations of the target architecture. We analyze the performance trade-offs and illustrate its benefits using several benchmarks and real-world workloads when temporarily boosting selected cores executing time-critical operations. While our study primarily focuses on AMD's architecture, we also provide a comparative evaluation of the features, limitations, and runtime overheads of both Turbo Boost and Turbo CORE technologies. Our results show that we can successful exploit these new hardware facilities to accelerate the execution of key sections of code (critical paths) improving overall performance of some multi-threaded applications. Unlike prior research, we focus on performance instead of power conservation. Our results further can give guidelines for the design of hardware power management facilities and the operating system interfaces to those facilities.
Miftakhutdinov, Rustam Raisovich
28 October 2014
This dissertation proves the feasibility of accurate runtime prediction of processor performance under frequency scaling. The performance predictors developed in this dissertation allow processors capable of dynamic voltage and frequency scaling (DVFS) to improve their performance or energy efficiency by dynamically adapting chip or core voltages and frequencies to workload characteristics. The dissertation considers three processor configurations: the uniprocessor capable of chip-level DVFS, the private cache chip multiprocessor capable of per-core DVFS, and the shared cache chip multiprocessor capable of per-core DVFS. Depending on processor configuration, the presented performance predictors help the processor realize 72–85% of average oracle performance or energy efficiency gains. / text
28 July 2011
In modern life, 3D graphics system is widely applied to portable product like Notebook, PDA and smart phone. Unlike desktop system, the capacity of batteries of these embedded systems is finite. Furthermore, rapid improvement of IC process leads to quick growth in the transistor count of a chip. According to above-mentioned reason and the complex computation of 3D graphics system, the power consumption will be very large. To efficiently lengthen the lifetime of battery, power management is an indispensable technique. Dynamic voltage and frequency scaling (DVFS) is one of the popular power management policy. In the scheme of DVFS, an accurate workload predictor is needed to predict the workload of every frame. According to these predictions a specific voltage and frequency level is applied to each frame of the 3D graphics system. The number of the voltage/frequency levels and the voltage/frequency of each level are fixed, the voltage/frequency table is decided according to the application of power management. Whenever the workload predictor completes the workload prediction of next frame, the voltage/frequency level of next frame will be found by looking up the voltage/frequency table. In this thesis, we propose a power management scheme with a framework composed of mainly Kalman filter and an auxiliary fuzzy controller to predict the workload of next frame. This scheme amends the shortcomings of traditional Kalman filter that needs to know the system features beforehand. And we propose a brand new concept named ¡¨delayed display¡¨ to massively reduce the miss rate of prediction without changing the framework of predictor.
An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-ChipYeh, Jia-huei 02 August 2010 (has links)
As time goes by rapid development of 3D graphics technique and 3C portable product output, 3D graphics have been widely applied to handheld devices, such as notebooks, PDAs, and smart cellular phones. Generally, to process 3D graphics applications in mobile devices, processor needs strong capability of handling large computational-intensive workloads. Complex computation consumes a great quantity of electric power. But the lifetime of handheld device battery is limited. Therefore, the cost, to satisfy this demand, will be shortening the supply time of device battery. Moreover, Moore¡¦ law said that the number of transistors in a chip is double in every eighteen months. But these days the advance in manufacturing batteries still cannot get up with the advance in developing processors. In addition, the improvement of chip size has led to more small, supply voltage of kernel processor in portable device. Considering system efficiency and battery lifetime simultaneously increase the difficulty of designing power management scheme. So, how to manage power effectively has become one of the important key for designing handheld products. For 3D graphics system, dynamic voltage and frequency scaling (DVFS) is one of good solutions to implement power management policy. DVFS needs an efficient online prediction method to predict the workload of frames and then appropriately adjust voltage and frequency for saving energy consumption. Consequently, a lot of related papers have proposed different prediction policy to predict the executing workload of 3D graphics system. For instance, the existing prediction policies include signature-based, history-based and proportion-integral-derivative (PID) methods, but most of designers put power management in software, i.e. processors. This solution not only slows power management to get the information about executing time of graphic processing unit (GPU), but also increases the operating overhead of CPU in handheld system. In this paper, we propose a power management workload prediction scheme with a framework of using proportion-integral (PI) controller to be a master controller and fuzzy controller to be a slave controller, and then implement it into hardware circuit. Taking advantage of fuzzy conception in fuzzy controller is to adjust the proportional parameter in PI controller, the shortage of traditional PI controller that demands on complicated try-and-error method to look for a good proportional and integral parameters can be avoided so that the adaption and forecasting accuracy can be improved. Besides, Uniform Window-size Predictor 1 (UW1) is also implemented as an assistant manner. Using UW1 predictor appropriately can improve the prediction trend to catch up with the trend of real workload. Experimental results show that our predictor improves prediction accuracy about 3.8% on average and saves about 0.02% more energy compared with PI predictor. Circuit area and power consumption only increases 6.8% percent and 1.4% compared with PI predictor. Besides, we also apply our predictor to the 3D first person game, Quake II, in the market. The result shows that our predictor is indeed an effective prediction policy. The adaption can put up with the intense workload variation of real game and adjust voltage and frequency precisely to decrease power consumption and meet the purpose of energy saving.
01 January 2006
In modern digital audio applications, a continuous audio signal stream is sampled at a fixed sampling rate, which is always greater than twice the highest frequency of the input signal, to prevent aliasing. A more energy efficient approach is to dynamically change the sampling rate based on the input signal. In the dynamic sampling rate technique, fewer samples are processed when there is little frequency content in the samples. The perceived quality of the signal is unchanged in this technique. Processing fewer samples involves less computation work; therefore processor speed and voltage can be reduced. This reduction in processor speed and voltage has been shown to reduce power consumption by up to 40% less than if the audio stream had been run at a fixed sampling rate.
Tapou, Monaf Sabri
In this thesis a design for a smart high efficiency voltage regulating module capable of supplying the core of modern microprocessors incorporating dynamic voltage and frequency scaling (DVS) capability is accomplished using a RISC based microcontroller to facilitate all the functions required to control, protect, and supply the core with the required variable operating voltage as set by the DVS management system. Normally voltage regulating modules provide maximum power efficiency at designed peak load, and the efficiency falls off as the load moves towards lesser values. A mathematical model has been derived for the main converter and small signal analysis has been performed in order to determine system operation stability and select a control scheme that would improve converter operation response to transients and not requiring intense computational power to realize. A Simulation model was built using Matlab/Simulink and after experimenting with tuned PID controller and fuzzy logic controllers, a simple fuzzy logic control scheme was selected to control the pulse width modulated converter and several methods were devised to reduce the requirements for computational power making the whole system operation realizable using a low power RISC based microcontroller. The same microcontroller provides circuit adaptations operation in addition to providing protection to load in terms of over voltage and over current protection. A novel circuit technique and operation control scheme enables the designed module to selectively change some of the circuit elements in the main pulse width modulated buck converter so as to improve efficiency over a wider range of loads. In case of very light loads as the case when the device goes into standby, sleep or hibernation mode, a secondary converter starts operating and the main converter stops. The secondary converter adapts a different operation scheme using switched capacitor technique which provides high efficiency at low load currents. A fuzzy logic control scheme was chosen for the main converter for its lighter computational power requirement promoting implementation using ultra low power embedded controllers. Passive and active components were carefully selected to augment operational efficiency. These aspects enabled the designed voltage regulating module to operate with efficiency improvement in off peak load region in the range of 3% to 5%. At low loads as the case when the computer system goes to standby or sleep mode, the efficiency improvent is better than 13% which will have noticeable contribution in extending battery run time thus contributing to lowering the carbon footprint of human consumption.
24 March 2011
The goal of this project is to develop a flexible multi-core hardware test-bed on field programmable gate array (FPGA) that can be used to effectively validate the theoretical research on multi-core computing, especially for the power/thermal aware computing. Based on a commercial FPGA test platform, i.e. Xilinx Virtex5 XUPV5 LX110T, we develop a homogeneous multi-core test-bed with four software cores, each of which can dynamically adjust its performance using software. We also enhance the operating system support for this test platform with the development of hardware and software primitives that are useful in dealing with inter-process communication, synchronization, and scheduling for processes on multiple cores. An application based on matrix addition and multiplication on multi-core is implemented to validate the applicability of the test bed.
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