This dissertation explores several challenges that plague the hardware-software co-design of popular resource constrained real-time embedded systems. We specifically tackle existing real-world problems, and address them through our design solutions which are highly scalable, and have practical feasibility as verified through our solution implementation on real-world hardware. We address the problem of poor battery life in mobile embedded devices caused due to side-by-side execution of multiple applications in split-screen mode. Existing industry solutions either restricts the number of applications that can run simultaneously, limit their functionality, and/or increase the hardware capacity of the battery associated with the system. We exploit the gap in research on performance and power trade-off in smartphones to propose an integrated energy management solution, that judiciously minimizes the system-wide energy consumption with negligible effect on its quality of service (QoS). Another important real-world requirement in today's interconnected world is the need for security. In the domain of real-time computing, it is not only necessary to secure the system but also maintain its timeliness. Some example security mechanisms that may be used in a hard real-time system include, but are not limited to, security keys, protection of intellectual property (IP) of firmware and application software, one time password (OTP) for software certification on-the-fly, and authenticated computational off-loading. Existing design solutions require expensive, custom-built hardware with long time-to-market or time-to-deployment cycle. A readily available alternative is the use of trusted execution environment (TEE) on commercial off-the-shelf (COTS) embedded processors. However, utilizing TEE creates multiple challenges from a real-time perspective, which includes additional time overhead resulting in possible deadline misses. Second, trusted execution may adversely affect the deterministic execution of the system, as tasks running inside a TEE may need to communicate with other tasks that are executing on the native real-time operating system. We propose three different solutions to address the need for a new task model that can capture the complex relationship between performance and predictability for real-time tasks that require secure execution inside TEE. We also present novel task assignment and scheduling frameworks for real-time trusted execution on COTS processors to improve task set schedulability. We extensively assess the pros and cons of our proposed approaches in comparison to the state-of-the-art techniques in custom-built real-world hardware for feasibility, and simulated environments to test our solutions' scalability. / Doctor of Philosophy / Today's real-world problems demand real-time solutions. These solutions need to be practically feasible, and scale well with increasing end user demands. They also need to maintain a balance between system performance and predictability, while achieving minimum energy consumption. A recent example of technological design problem involves ways to improve the battery lifetime of mobile embedded devices, for example, smartphones, while still achieving the required performance objectives. For instance, smartphones that run Android OS has the capability to run multiple applications concurrently using a newly introduced split-screen mode of execution, where applications can run side-by-side at the same time on screen while using the same shared resources (e.g., CPU, memory bandwidth, peripheral devices etc.). While this can improve the overall performance of the system, it can also lead to increased energy consumption, thereby directly affecting the battery life. Another technological design problem involves ways to protect confidential proprietary information from being siphoned out of devices by external attackers. Let us consider a surveillance unmanned aerial vehicle (UAV) as an example. The UAV must perform sensitive tasks, such as obtaining coordinates of interest for surveillance, within a given time duration, also known as task deadline. However, an attacker may learn how the UAV communicates with ground control, and take control of the UAV, along with the sensitive information it carries. Therefore, it is crucial to protect such sensitive information from access by an unauthorized party, while maintaining the system's task deadlines. In this dissertation, we explore these two real-world design problems in depth, observe the challenges associated with them, while presenting several solutions to tackle the issues. We extensively assess the pros and cons of our proposed approaches in comparison to the state-of- the-art techniques in custom-built real-world hardware, and simulated environments to test our solutions' scalability.

Esta tese avalia os benefícios e desafios associados com a operação em uma ampla faixa de frequências e tensões próximas ao limiar do transistor. A diminuição da tensão de alimentação em circuitos digitais CMOS apresenta grandes vantagens em termos de potência consumida pelo circuito. Esta diminuição da potência é acompanhada por uma redução da performance, reflexo da diminuição na tensão de alimentação. A operação de circuitos digitais no ponto de energia mínima é comumente associada ao regime de operação abaixo do limiar do transistor, trazendo enormes penalidades em performance e variabilidade. Esta dissertação mostra que é possível obter 8X mais eficiência energética com uma ampla faixa dinâmica de tensão e frequência, da tensão nominal até o limite inferior da operação próximo ao limiar do transistor. Como parte deste estudo, uma biblioteca de células digitais CMOS para esta ampla faixa de frequências foi desenvolvida. A biblioteca de células lógicas foi exercitada em um PDK comercial de 65nm para operação próximo ao limiar do transistor, reduzindo os efeitos da variabilidade sem comprometer o projeto em termos de área e energia quando operando em inversão forte. Para operar próximo e abaixo do limiar do transistor as células devem ser desenvolvidas com um número limitado de transistores em série. Nosso estudo mostra que uma performance aceitável em termos de margens de ruído estático é obtida para um conjunto restrito de células, onde são empregados no máximo dois transistores em série. Reportamos resultados para projetos de média complexidade que incluem um filtro notch de 25kgates, um microcontrolador 8051 de 20kgates, e 4 circuitos combinacionais/ sequenciais do conjunto de avaliação ISCAS. Neste trabalho, é estudada a máxima frequência atingida em cada tensão de alimentação, desde 0.15V até 1.2V. O ponto de mínima energia é demonstrado em operação abaixo do limiar do transistor, aproximadamente 0.29V, oque representa um ganho de 2X em eficiência energética comparado ao regime de operação próximo ao limiar do transistor. Embora o pico de eficiência energética ocorra abaixo do limiar do transistor para os circuitos estudados, nós também demonstramos que nesta tensão de alimentação ultra-baixa o atraso e a potência sofrem um impacto substancial devido ao aumento na variabilidade, atigindo uma degradação em performance de 30X, com respeito à operação próxima ao limiar do transistor. / This thesis assesses the benefits and drawbacks associated with a very wide range of frequency when operation at near-threshold is considered. Scaling down the supply voltage in digital CMOS circuits presents great benefits in terms of power reduction. Such scaling comes with a performance penalty, hence in digital synchronous circuits the reduction in frequency of operation follows, for a given circuit layout, the VDD reduction. Minimum-energy operation of digital CMOS circuits is commonly associated to the sub-VT regime, carrying huge performance and variability penalties. This thesis shows that it is possible to achieve 8X higher energy-efficiency with a very-wide range of dynamic voltage-frequency scaling, from nominal voltages down to the lower boundary of near-VT operation. As part of this study, a CMOS digital cell-library for such wide range of frequencies was developed. The cell-library is exercised in a 65nm commercial PDK and targets near-VT operation, mitigating the variability effects without compromising the design in terms of area and energy at strong inversion. For near-VT or sub-VT operation the cells have to be designed with few stacked transistors. Our study shows that acceptable performance in terms of static-noise margins is obtained for a constrained set of cells, for which a maximum of 2-stacked transistors are allowed. In this set we include master-slave registers. We report results for medium complexity designs which include a 25kgates notch filter, a 20kgates 8051 compatible core, and 4-combinational/4-sequential ISCAS benchmark circuits. In this work the maximum frequency attainable at each supply for a wide variation of voltage is studied from 150mV up to nominal voltage (1.2V). The sub-VT operation is shown to hold the minimum energy-point at roughly 0.29V, which represents a 2X energy-saving compared to the near-VT regime. Although energy-efficiency peaks in sub-VT for the circuits studied, we also show that in this ultra-low VDD the circuit timing and power suffer from substantially increased variability impact and a 30X performance drawback, with respect to near-VT.

As time goes by rapid development of 3D graphics technique and 3C portable product output, 3D graphics have been widely applied to handheld devices, such as notebooks, PDAs, and smart cellular phones. Generally, to process 3D graphics applications in mobile devices, processor needs strong capability of handling large computational-intensive workloads. Complex computation consumes a great quantity of electric power. But the lifetime of handheld device battery is limited. Therefore, the cost, to satisfy this demand, will be shortening the supply time of device battery. Moreover, Moore¡¦ law said that the number of transistors in a chip is double in every eighteen months. But these days the advance in manufacturing batteries still cannot get up with the advance in developing processors. In addition, the improvement of chip size has led to more small, supply voltage of kernel processor in portable device. Considering system efficiency and battery lifetime simultaneously increase the difficulty of designing power management scheme. So, how to manage power effectively has become one of the important key for designing handheld products. For 3D graphics system, dynamic voltage and frequency scaling (DVFS) is one of good solutions to implement power management policy. DVFS needs an efficient online prediction method to predict the workload of frames and then appropriately adjust voltage and frequency for saving energy consumption. Consequently, a lot of related papers have proposed different prediction policy to predict the executing workload of 3D graphics system. For instance, the existing prediction policies include signature-based[1], history-based[3] and proportion-integral-derivative (PID)[14] methods, but most of designers put power management in software, i.e. processors. This solution not only slows power management to get the information about executing time of graphic processing unit (GPU), but also increases the operating overhead of CPU in handheld system. In this paper, we propose a power management workload prediction scheme with a framework of using proportion-integral (PI) controller to be a master controller and fuzzy controller to be a slave controller, and then implement it into hardware circuit. Taking advantage of fuzzy conception in fuzzy controller is to adjust the proportional parameter in PI controller, the shortage of traditional PI controller that demands on complicated try-and-error method to look for a good proportional and integral parameters can be avoided so that the adaption and forecasting accuracy can be improved. Besides, Uniform Window-size Predictor 1 (UW1) is also implemented as an assistant manner. Using UW1 predictor appropriately can improve the prediction trend to catch up with the trend of real workload. Experimental results show that our predictor improves prediction accuracy about 3.8% on average and saves about 0.02% more energy compared with PI predictor[18]. Circuit area and power consumption only increases 6.8% percent and 1.4% compared with PI predictor. Besides, we also apply our predictor to the 3D first person game, Quake II, in the market. The result shows that our predictor is indeed an effective prediction policy. The adaption can put up with the intense workload variation of real game and adjust voltage and frequency precisely to decrease power consumption and meet the purpose of energy saving.

In modern life, 3D graphics system is widely applied to portable product like Notebook, PDA and smart phone. Unlike desktop system, the capacity of batteries of these embedded systems is finite. Furthermore, rapid improvement of IC process leads to quick growth in the transistor count of a chip. According to above-mentioned reason and the complex computation of 3D graphics system, the power consumption will be very large. To efficiently lengthen the lifetime of battery, power management is an indispensable technique. Dynamic voltage and frequency scaling (DVFS) is one of the popular power management policy. In the scheme of DVFS, an accurate workload predictor is needed to predict the workload of every frame. According to these predictions a specific voltage and frequency level is applied to each frame of the 3D graphics system. The number of the voltage/frequency levels and the voltage/frequency of each level are fixed, the voltage/frequency table is decided according to the application of power management. Whenever the workload predictor completes the workload prediction of next frame, the voltage/frequency level of next frame will be found by looking up the voltage/frequency table. In this thesis, we propose a power management scheme with a framework composed of mainly Kalman filter and an auxiliary fuzzy controller to predict the workload of next frame. This scheme amends the shortcomings of traditional Kalman filter that needs to know the system features beforehand. And we propose a brand new concept named ¡¨delayed display¡¨ to massively reduce the miss rate of prediction without changing the framework of predictor.

Esta tese avalia os benefícios e desafios associados com a operação em uma ampla faixa de frequências e tensões próximas ao limiar do transistor. A diminuição da tensão de alimentação em circuitos digitais CMOS apresenta grandes vantagens em termos de potência consumida pelo circuito. Esta diminuição da potência é acompanhada por uma redução da performance, reflexo da diminuição na tensão de alimentação. A operação de circuitos digitais no ponto de energia mínima é comumente associada ao regime de operação abaixo do limiar do transistor, trazendo enormes penalidades em performance e variabilidade. Esta dissertação mostra que é possível obter 8X mais eficiência energética com uma ampla faixa dinâmica de tensão e frequência, da tensão nominal até o limite inferior da operação próximo ao limiar do transistor. Como parte deste estudo, uma biblioteca de células digitais CMOS para esta ampla faixa de frequências foi desenvolvida. A biblioteca de células lógicas foi exercitada em um PDK comercial de 65nm para operação próximo ao limiar do transistor, reduzindo os efeitos da variabilidade sem comprometer o projeto em termos de área e energia quando operando em inversão forte. Para operar próximo e abaixo do limiar do transistor as células devem ser desenvolvidas com um número limitado de transistores em série. Nosso estudo mostra que uma performance aceitável em termos de margens de ruído estático é obtida para um conjunto restrito de células, onde são empregados no máximo dois transistores em série. Reportamos resultados para projetos de média complexidade que incluem um filtro notch de 25kgates, um microcontrolador 8051 de 20kgates, e 4 circuitos combinacionais/ sequenciais do conjunto de avaliação ISCAS. Neste trabalho, é estudada a máxima frequência atingida em cada tensão de alimentação, desde 0.15V até 1.2V. O ponto de mínima energia é demonstrado em operação abaixo do limiar do transistor, aproximadamente 0.29V, oque representa um ganho de 2X em eficiência energética comparado ao regime de operação próximo ao limiar do transistor. Embora o pico de eficiência energética ocorra abaixo do limiar do transistor para os circuitos estudados, nós também demonstramos que nesta tensão de alimentação ultra-baixa o atraso e a potência sofrem um impacto substancial devido ao aumento na variabilidade, atigindo uma degradação em performance de 30X, com respeito à operação próxima ao limiar do transistor. / This thesis assesses the benefits and drawbacks associated with a very wide range of frequency when operation at near-threshold is considered. Scaling down the supply voltage in digital CMOS circuits presents great benefits in terms of power reduction. Such scaling comes with a performance penalty, hence in digital synchronous circuits the reduction in frequency of operation follows, for a given circuit layout, the VDD reduction. Minimum-energy operation of digital CMOS circuits is commonly associated to the sub-VT regime, carrying huge performance and variability penalties. This thesis shows that it is possible to achieve 8X higher energy-efficiency with a very-wide range of dynamic voltage-frequency scaling, from nominal voltages down to the lower boundary of near-VT operation. As part of this study, a CMOS digital cell-library for such wide range of frequencies was developed. The cell-library is exercised in a 65nm commercial PDK and targets near-VT operation, mitigating the variability effects without compromising the design in terms of area and energy at strong inversion. For near-VT or sub-VT operation the cells have to be designed with few stacked transistors. Our study shows that acceptable performance in terms of static-noise margins is obtained for a constrained set of cells, for which a maximum of 2-stacked transistors are allowed. In this set we include master-slave registers. We report results for medium complexity designs which include a 25kgates notch filter, a 20kgates 8051 compatible core, and 4-combinational/4-sequential ISCAS benchmark circuits. In this work the maximum frequency attainable at each supply for a wide variation of voltage is studied from 150mV up to nominal voltage (1.2V). The sub-VT operation is shown to hold the minimum energy-point at roughly 0.29V, which represents a 2X energy-saving compared to the near-VT regime. Although energy-efficiency peaks in sub-VT for the circuits studied, we also show that in this ultra-low VDD the circuit timing and power suffer from substantially increased variability impact and a 30X performance drawback, with respect to near-VT.

Esta tese avalia os benefícios e desafios associados com a operação em uma ampla faixa de frequências e tensões próximas ao limiar do transistor. A diminuição da tensão de alimentação em circuitos digitais CMOS apresenta grandes vantagens em termos de potência consumida pelo circuito. Esta diminuição da potência é acompanhada por uma redução da performance, reflexo da diminuição na tensão de alimentação. A operação de circuitos digitais no ponto de energia mínima é comumente associada ao regime de operação abaixo do limiar do transistor, trazendo enormes penalidades em performance e variabilidade. Esta dissertação mostra que é possível obter 8X mais eficiência energética com uma ampla faixa dinâmica de tensão e frequência, da tensão nominal até o limite inferior da operação próximo ao limiar do transistor. Como parte deste estudo, uma biblioteca de células digitais CMOS para esta ampla faixa de frequências foi desenvolvida. A biblioteca de células lógicas foi exercitada em um PDK comercial de 65nm para operação próximo ao limiar do transistor, reduzindo os efeitos da variabilidade sem comprometer o projeto em termos de área e energia quando operando em inversão forte. Para operar próximo e abaixo do limiar do transistor as células devem ser desenvolvidas com um número limitado de transistores em série. Nosso estudo mostra que uma performance aceitável em termos de margens de ruído estático é obtida para um conjunto restrito de células, onde são empregados no máximo dois transistores em série. Reportamos resultados para projetos de média complexidade que incluem um filtro notch de 25kgates, um microcontrolador 8051 de 20kgates, e 4 circuitos combinacionais/ sequenciais do conjunto de avaliação ISCAS. Neste trabalho, é estudada a máxima frequência atingida em cada tensão de alimentação, desde 0.15V até 1.2V. O ponto de mínima energia é demonstrado em operação abaixo do limiar do transistor, aproximadamente 0.29V, oque representa um ganho de 2X em eficiência energética comparado ao regime de operação próximo ao limiar do transistor. Embora o pico de eficiência energética ocorra abaixo do limiar do transistor para os circuitos estudados, nós também demonstramos que nesta tensão de alimentação ultra-baixa o atraso e a potência sofrem um impacto substancial devido ao aumento na variabilidade, atigindo uma degradação em performance de 30X, com respeito à operação próxima ao limiar do transistor. / This thesis assesses the benefits and drawbacks associated with a very wide range of frequency when operation at near-threshold is considered. Scaling down the supply voltage in digital CMOS circuits presents great benefits in terms of power reduction. Such scaling comes with a performance penalty, hence in digital synchronous circuits the reduction in frequency of operation follows, for a given circuit layout, the VDD reduction. Minimum-energy operation of digital CMOS circuits is commonly associated to the sub-VT regime, carrying huge performance and variability penalties. This thesis shows that it is possible to achieve 8X higher energy-efficiency with a very-wide range of dynamic voltage-frequency scaling, from nominal voltages down to the lower boundary of near-VT operation. As part of this study, a CMOS digital cell-library for such wide range of frequencies was developed. The cell-library is exercised in a 65nm commercial PDK and targets near-VT operation, mitigating the variability effects without compromising the design in terms of area and energy at strong inversion. For near-VT or sub-VT operation the cells have to be designed with few stacked transistors. Our study shows that acceptable performance in terms of static-noise margins is obtained for a constrained set of cells, for which a maximum of 2-stacked transistors are allowed. In this set we include master-slave registers. We report results for medium complexity designs which include a 25kgates notch filter, a 20kgates 8051 compatible core, and 4-combinational/4-sequential ISCAS benchmark circuits. In this work the maximum frequency attainable at each supply for a wide variation of voltage is studied from 150mV up to nominal voltage (1.2V). The sub-VT operation is shown to hold the minimum energy-point at roughly 0.29V, which represents a 2X energy-saving compared to the near-VT regime. Although energy-efficiency peaks in sub-VT for the circuits studied, we also show that in this ultra-low VDD the circuit timing and power suffer from substantially increased variability impact and a 30X performance drawback, with respect to near-VT.

No description available.

Η σύγχρονη αρχιτεκτονική στρέφεται σε λύσεις που έχουν ως στόχο την εξοικονόμηση ενέργειας, χωρίς όμως να επιβαρύνεται σε μεγάλο βαθμό η απόδοση του επεξεργαστή. Ιδιαίτερα οι υπερβαθμωτοί (superscalar) επεξεργαστές που επιτρέπουν εκτέλεση εκτός σειράς (out-of-order execution) διακρίνονται από υψηλή κατανάλωση ενέργειας, εξαιτίας των πολύπλοκων δομών που χρησιμοποιούν για την αύξηση της απόδοσης. Η δυναμική ρύθμιση τάσης – συχνότητας (DVFS) αποτελεί μία ευρέως χρησιμοποιούμενη τεχνική για την επίτευξη εξοικονόμησης ενέργειας. Μειώνοντας τη συχνότητα λειτουργίας ενός κυκλώματος, είναι δυνατόν να μειωθεί και η τάση τροφοδοσίας του κυκλώματος. Με τον τρόπο αυτό ελαττώνεται και η ενέργεια που καταναλώνει το κύκλωμα. Σκοπός της εργασίας είναι η ανάπτυξη ενός μηχανισμού πραγματικού χρόνου που θα ρυθμίζει τη συχνότητα και την τάση λειτουργίας ενός superscalar, out-of-order επεξεργαστή ώστε να επιτυγχάνεται εξοικονόμηση ενέργειας χωρίς μεγάλη μείωση της απόδοσης του επεξεργαστή. Αυτό μπορεί να επιτευχθεί ελαττώνοντας τη συχνότητα και την τάση κατά τις περιόδους που ο επεξεργαστής εκτελεί πολλές λειτουργίες μνήμης. Η εξομοίωση του μηχανισμού μας για μία σειρά από μετροπρογράμματα δείχνει ότι μπορούμε να επιτύχουμε μεγάλη εξοικονόμηση ενέργειας χωρίς σημαντική αύξηση του χρόνου εκτέλεσης των προγραμμάτων. / Modern research in computer architecture focuses on techniques whose purpose is to save energy, without much loss in processor's performance. Especially superscalar processors that allow out of order execution are characterized by high energy consumption, because of the complex structures the use in order to increase performance. Dynamic Voltage - Frequency Scaling (DVFS) is a widely used technique for energy saving. Reducing the frequency of the processor's clock, it is possible to reduce the supply voltage. In this way the consumed energy is also reduced. The purpose of this diploma thesis is to create a real time mechanism that will scale the frequency and the voltage of a superscalar, out of order processor so that the processor saves energy without much loss in processor's performance. This can be made by reducing the frequency and the voltage during the periods that the processor executes many memory functions. The simulation of our mechanism for a variety of benchmarks proved that we can save much energy without much increase in the benchmark's execution time.

abstract: Semiconductor scaling technology has led to a sharp growth in transistor counts. This has resulted in an exponential increase on both power dissipation and heat flux (or power density) in modern microprocessors. These microprocessors are integrated as the major components in many modern embedded devices, which offer richer features and attain higher performance than ever before. Therefore, power and thermal management have become the significant design considerations for modern embedded devices. Dynamic voltage/frequency scaling (DVFS) and dynamic power management (DPM) are two well-known hardware capabilities offered by modern embedded processors. However, the power or thermal aware performance optimization is not fully explored for the mainstream embedded processors with discrete DVFS and DPM capabilities. Many key problems have not been answered yet. What is the maximum performance that an embedded processor can achieve under power or thermal constraint for a periodic application? Does there exist an efficient algorithm for the power or thermal management problems with guaranteed quality bound? These questions are hard to be answered because the discrete settings of DVFS and DPM enhance the complexity of many power and thermal management problems, which are generally NP-hard. The dissertation presents a comprehensive study on these NP-hard power and thermal management problems for embedded processors with discrete DVFS and DPM capabilities. In the domain of power management, the dissertation addresses the power minimization problem for real-time schedules, the energy-constrained make-span minimization problem on homogeneous and heterogeneous chip multiprocessors (CMP) architectures, and the battery aware energy management problem with nonlinear battery discharging model. In the domain of thermal management, the work addresses several thermal-constrained performance maximization problems for periodic embedded applications. All the addressed problems are proved to be NP-hard or strongly NP-hard in the study. Then the work focuses on the design of the off-line optimal or polynomial time approximation algorithms as solutions in the problem design space. Several addressed NP-hard problems are tackled by dynamic programming with optimal solutions and pseudo-polynomial run time complexity. Because the optimal algorithms are not efficient in worst case, the fully polynomial time approximation algorithms are provided as more efficient solutions. Some efficient heuristic algorithms are also presented as solutions to several addressed problems. The comprehensive study answers the key questions in order to fully explore the power and thermal management potentials on embedded processors with discrete DVFS and DPM capabilities. The provided solutions enable the theoretical analysis of the maximum performance for periodic embedded applications under power or thermal constraints. / Dissertation/Thesis / Ph.D. Computer Science 2012

Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP). / This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).