arket forces are continually demanding devices with increased functionality/unit area; these demands have been satisfied through aggressive technology scaling which, unfortunately, has impacted adversely on the global interconnect delay subsequently reducing system performance. Line drivers have been used to mitigate the problems with delay; however, these have a large power consumption. A solution to reducing the power dissipation of the drivers is to use lower supply voltages. However, by adopting a lower power supply voltage, the performance of the line drivers for global interconnects is impaired unless low-swing signalling techniques are implemented. Low-swing signalling techniques can provide high speed signalling with low power consumption and hence can be used to drive global on-chip interconnect. Most of the proposed low-swing signalling schemes are immune to noise as they have a good SNR. However, they tend to have a large penalty in area and complexity as they require additional circuitry such as voltage generators and low-Vth devices. Most of the schemes also incorporate multiple Vdd and reference voltages which increase the overall circuit complexity. A diode-connected driver circuit has the best attributes over other low-swing signalling techniques in terms of low power, low delay, good SNR and low area overhead. By incorporating a diode-connected configuration at the output, it can provide high speed signalling due to its high driving capability. However, this configuration also has its limitations as it has issues with its adaptability to process variations, as well as an issue with leakage currents. To address these limitations, two novel driver schemes have been designed, namely, nLVSD and mLVSD, which, additionally, have improvements in performance and power consumption. Comparisons between the proposed schemes with the existing diode-connected driver circuits (MJ and DDC) showed that the nLVSD and mLVSD drivers have approximately 46% and 50% less delay. The name MJ originates from the driver’s designer called Juan A. Montiel-Nelson, while DDC stands for dynamic diode-connected. In terms of power consumption, the nLVSD and mLVSD drivers also produce 43% and 7% improvement. Additionally, the mLVSD driver scheme is the most robust as its SNR is 14 to 44% higher compared to other diode-connected driver circuits. On the other hand, the nLVSD driver has 6% lower SNR compared to the MJ driver, even though it is 19% more robust than the DDC driver. However, since its SNR is still above 1, its improved performance and reduced power consumption, as well other advantages it has over other diode-connected driver circuits can compensate for this limitation. Regarding the robustness to external disturbances, the proposedmdriver circuits are more robust to crosstalk effects as the nLVSD and mLVSD drivers are approximately 35% and 7% more robust than other diode-connected drivers. Furthermore, the mLVSD driver is 5%, 33% and 47% more tolerant to SEUs compared to the nLVSD, MJ and DDC driver circuits respectively, whilst the MJ and DDC drivers are 26% and 40% less tolerant to SEUs iii compared to the nLVSD circuit. A comparison between the four schemes was also undertaken in the presence of ±3σ process and voltage (PV) variations. The analysis indicated that both proposed driver schemes are more robust than other diode-connected driver schemes, namely, the MJ and DDC driver circuits. The MJ driver scheme deviates approximately 18% and 35% more in delay and power consumption compared to the proposed schemes. The DDC driver has approximately 20% and 57% more variations in delay and power consumption in comparison to the proposed schemes. In order to further improve the robustness of the proposed driver circuits against process variation and environmental disturbances, they were further analysed to identify which process variables had the most impact on circuit delay and power consumption, as well as identifying several design techniques to mitigate problems with environmental disturbances. The most significant process parameters to have impact on circuit delay and power consumption were identified to be Vdd, tox, Vth, s, w and t. The impact of SEUs on the circuit can be reduced by increasing the bias currents whilst design methods such as increasing the interconnect spacing can help improve the circuit robustness against crosstalk. Overall it is considered that the proposed nLVSD and mLVSD circuits advance the state of the art in driver design for on-chip signalling applications.

New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with Partial Dynamic Reconfiguration (PDR). The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this thesis. At the architecture level a configurable router is proposed that supports dynamically reconfigurable networks. This router uses distributed routing for regular and irregular topologies and can vary the number of local ports and communication ports to build multi-dimensional networks with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports per router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port per router. To complete this network architecture a routing algorithm is investigated capable of supporting topologies based on a variable number and size of innertorus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The subnetworks can generate irregular global topologies which are also supported by the routing algorithm . This routing algorithm supports the addition of links to the mesh topology at run-time to reduce congestion depending on the application behaviour and resource availability. The proposed routing algorithm allows the insertion of links as requested by different parts of the application without centralised control. The analysis shows that despite this dynamic behaviour the routing algorithm remains deadlock free .

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