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Hardware acceleration is becoming increasingly important in high performance applications due to their computational complexity. Recently, field programmable gate arrays (FPGAs) have gained popularity as a suitable platform for many high performance applications. FPGAs offer low power, reconfigurability, high performance and low design- turnaround time which enable FPGAs to be used in a number of image and signal processing applications. Due to the increasing complexity of acceleration systems, abstraction of these technologies and power dissipation has become one of the most important challenges. Addressing these issues require awareness at all levels of the system and FPGA design flow. The key achievements of the work presented in this thesis are summarised as follows. Novel architectures based on different design approaches and abstraction techniques - virtual file systems (VFS), dynamic partial reconfiguration (DPR) mechanism, distributed arithmetic (DA) and parallel digital signal processing - are developed for a generic frame- work and for three-dimensional (3-D) algorithms. Furthermore, solutions to divide large algorithms into small modules that fit on smaller, less power consuming FPGAs are investigated. An abstraction layer using a VFS for different platforms is carried out, and as a result a partial reconfiguration design flow framework is developed. The ultimate aim of this dissertation is to examine an efficient reconfigurable architecture for generic 3-D cyclic convolution (3-DeC). This is achieved with the previously investigated abstraction layer and framework, to demonstrate the operation of the framework, allowing discussion and the evaluation of techniques that are only possible on new FPGA devices. Results obtained have shown the advantages offered by the DPR framework and abstraction layer, and lead to a processing solution for implementing computationally intensive applications. A key section of this work included the development of the complete integration of the dynamic partial reconfiguration design flow and application usage - using the proposed abstraction model. The technique used explores the logic space and power consumptions needed to divide the algorithm for optimal application runtime situations.

This project aims to construct logical circuits in models of chemical media, including two cellular automata models: the 2+ -medium and the spiral rule, as well as a numerical simulation model of the light-sensitive Belousov-Zhabotinsky (BZ) medium. The 2+ -medium is a two-dimensional three-state cellular automaton model of the excitable medium. Each cell takes one of the three possible states: excited, refractory and resting. All cells update their states simultaneously in discrete time depending on the states of its eight neighbours. A resting cell becomes excited if it has exactly two excited neighbours, and the transitions from excited state to refractory state, and from refractory state to resting state are unconditional. Binary adders and multipliers are implemented in the 2+ -medium . The spiral rule is a three-state k-totalistic cellular automaton on a two-dimensional lattice with hexagonal tiling. Each cell has three possible states: 0, 1 and 2, and a 7- cell neighbourhood consisting of the cell itself as well as its six closest neighbours. The spiral rule can also be interpreted as a model of reaction-diffusion chemical system. Many structures emerge while evolving the spiral rule, including gliders, stationary eaters and glider guns. Binary counters and adders are implemented in the spiral rule. The light-sensitive ruthenium-catalysed BZ medium has a feature that its excitability can be controlled by adjusting the light intensity. While the excitability is in the sub-excitable state, wave-fragments can be initiated, providing a means to perform collision-based computing in real chemical media. In this project, a two-variable Oregonator model is used to simulate such a medium. A 1-bit half adder is implemented in the simulated medium with wave-fragments constrained by channels.

Since the invention of FPGAs in 1984, their capabilities have increased dramatically making them more speed, area, and power efficient than older reconfigurable devices. These advances were made possible by better computer aided design tools and the continuous development of algorithms used to both design the chips, and to map circuits onto them. However, current methodologies for FPGA chip design suffer from their dependence on empirical approaches which sample the design space based on intuition and heuristic techniques. As a result these empirical tools might result in good architectures but their optimality cannot be measured. This thesis argues the case for the use of analytical models in heterogeneous FPGA architecture exploration. It shows that the problem, when simplified, is amenable to formal optimisation techniques such as Integer Linear Programming (ILP). However, the simplification process may lead to inaccurate models causing uncertainty about the quality of the results. Consequently, existing accurate models such as that used in the versatile place and route (VPR) tool are used to quantify the performance of the analytical framework in comparison with traditional design methodologies. The results obtained in this thesis show that the architectures found by the ILP model are better than those found using traditional parameter sweep techniques with an average improvement of up to 15% in speed. In addition, these architectures are further improved by combining the accuracy of VPR with the efficiency of analytical techniques. This was achieved using a closed loop framework which iteratively refines the analytical model using place and route information from VPR. The results show a further average improvement of 10% and a total improvement of 25% in comparison with a parameter sweep methodology. In summary, the work carried out in this thesis shows that the ILP architecture exploration framework may not model heterogeneous architectures as accurately as current place and route tools, however, it improves on parameter sweep techniques by exploring a wider range of designs.

Complex Systems can be seen in many important events and aspects of our world. However, their study is not a trivial task due to the multiple complications found to access some of these systems, the complex and convoluted network of connections between elements and the amount of elements involved in them. This study also affects engineered systems, which have become more complex due to an increase in their size and number of interactions between their elements, resulting in unexpected misbehaviour that may potentially alter the results of the system. A traditional top-down analytical approach is not enough to completely understand Complex Systems, and a bottom-up agent-based approach has been suggested to be used to model and simulate them. Reconfigurable Hardware represents a suitable platform for the natural implementation of Agent-based Systems, used in the simulations of Complex Systems, providing the parallelism and flexibility that other platforms lack. The main aim of the work in this thesis is to present a study of how to implement and what are the benefits of implementing Agent-based System using Reconfigurable Hardware. A static implementation takes advantage of the parallelism and flexibility of Reconfigurable Hardware to implement Agent-based Systems, using a flexible decentralised communication structure, which provides the elements of the system with the required level of flexibility in their interactions. A suitable communication structure simplifies the behaviour of the processing elements. A dynamic implementation exploits dynamic reconfiguration in order to create a dynamic architecture, which facilitates the implementation of the dynamic behaviour of the agents by adapting to changes in their interactions. The communication between elements is simplified and the efficiency and flexibility of the system increases. This thesis presents the suitability of both implementations in the design of simulations of Complex Systems, exploiting the parallelism and flexibility of Reconfigurable Hardware, using Reynolds' Boids as case study, and highlight the advantages and disadvantages of each approach.

Power amplifiers are key elements in the modern communication systems. They are used to generate the required power and amplify the signal to be transmitted. Linear and efficient amplifiers are needed in most of modern wireless systems. However, either linearity or efficiency will be compromised during amplifier design procedure. In order to meet these two requirement at the same time, linearisers are usually applied on the efficient but nonlinear amplifiers. This dissertation presents a study of a novel linearisation technique, based on the minimal control synthesis (MCS) algorithm. The objective of this work is to demonstrate the feasibility of this new linearisation approach. The aim is achieved by the simulation and implementation results. The MCS-based lineariser can be implemented on their own. Alternatively, the adaptive controllers can be retrofitted to existing, more conventional control schemes, e.g. pre-distortion lineariser and Cartesian feedback lineariser.

The fast progress in biological study has attracted a growing interest in mimicking the signal processing functions of biological neural systems, which can be implemented in hardware and used to inspire new techniques for real time computations. On the other hand, the ITRS roadmap for Si indicates that alternative paradigms for building computational machines will be required within about 10 years and the massive parallelism of neural systems represents an attractive option. However most implementation approaches are restrictive in physical dimensions and characteristics towards biological networks in hardware. Thus there is a pressing need for compact. low power neural building blocks with operational characteristics that closely mimic realistic neuron cells. In this thesis, a charge coupled synapse is developed as a core building block for spiking neural networks in hardware. The proposed silicon synapse is based on a two-phase charge transfer device with associated localized memory capability. The correspondence between the fundamental semiconductor processes and the required biological functionality is illustrated by theory.