Future Systems on Chip (SoCs) are likely to consist of many independent or semi-independent clock regions with the need to synchronize the data passing between them. Consequently, there will be many synchronizers together with interconnecting and routing elements forming an on-chip communication network.

This thesis explores methods to construct efficient wavelet transforms for operation on Field Programmable Gate Array (FPGA) devices. Additionally the wavelets designed have been used in an audio watermarking application.

Execution of Real Time simulation models is crucial in control systems but rarely achieved for highly complex feedback models. On the other hand, the use of Field Programmable Gate Arrays (FPGA) technology is proven to achieve execution speeds faster than real time for high fidelity models. However, as current FPGA applications are specialised and tool sets do not support basic control systems floating point blocks, significant effort is invested in order to incorporate new designs. These are typically non-intuitive, constructed and optimised manually. In order to overcome these difficulties, this thesis offers a standalone solution for simulation of control system designs using FPGAs. This is based on a floating point library of re-usable Hardware Descriptive Language (HDL) components, under System Generator toolbox, in Simulink. Also, extended research was performed in collaboration with Jaguar Land Rover, Rolls-Royce and Goodrich in order to underline general practices and main limitations of current methods found in Automotive and Aerospace Industries. The first contribution is a modelling design suite for floating point HDL control systems applications which reduces the design time to that of standard Simulink control systems simulation models. The most efficient FPGA design implementation is discussed. The presented methods are based on an extensive range of HDL design paths which assure the efficiency of the generated HDL structures, including comparisons not explored in the current literature. Contributions are offered for one of the major challenges found in generic FPGA implementations: the optimisation of the pipelining stages. A semi-automated throughput optimisation process was constructed on a rigorous mathematical model. Furthermore, the transition from serial to parallel architectures represents a considerable challenge due to an overwhelming number of unexplored options and conflicting factors. The work presented achieves the first reported complete parallelisation characterisation for generic MIMO L T1 state space systems using standalone FPGA implementations. This allows computational architectures to be split into most of the feasible combinations of serial and parallel FPGA computing blocks. Automatic optimisations of latency, occupied FPGA area and execution speed are attained and justified in respect to an increased number of possible implementations. These contributions are combined to offer a complete package for high fidelity control systems implementations. Results given by generic complex test case studies show a consistent execution time speed-up when compared to other industry based available technologies.

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This thesis addresses the use of reconfigurable hardware in computing platforms, in order to harness the performance benefits of dedicated hardware whilst maintaining the flexibility associated with software. Although the reconfigurable computing concept is not new, the low level nature of the supporting tools normally used, together with the consequent limited level of abstraction and resultant lack of backwards compatibility, has prevented the widespread adoption of this technology. In addition, bandwidth and architectural limitations, have seriously constrained the potential improvements in performance. A review of existing approaches and tools flows is conducted to highlight the current problems being faced in this field. The objective of the work presented in this thesis is to introduce a radically new approach to reconfigurable computing tool flows. The runtime based tool flow introduces complete abstraction between the application developer and the underlying hardware. This new technique eliminates the ease of use and backwards compatibility issues that have plagued the reconfigurable computing concept, and could pave the way for viable mainstream reconfigurable computing platforms. An easy to use, cycle accurate behavioural modelling system is also presented, which was used extensively during the early exploration of new concepts and architectures. Some performance improvements produced by the new reconfigurable computing tool flow, when applied to both a MIPS based embedded platform, and the Cray XDl, are also presented. These results are then analyzed and the hardware and software factors affecting the performance increases that were obtained are discussed, together with potential techniques that could be used to further increase the performance of the system. Lastly a heterogenous computing concept is proposed, in which, a computer system, containing multiple types of computational resource is envisaged, each having their own strengths and weaknesses (e.g. DSPs, CPUs, FPGAs). A revolutionary new method of fully exploiting the potential of such a system, whilst maintaining scalability, backwards compatibility, and ease of use is also presented.

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The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (such as processor cores and buses) should enforce the operation of the FPGA-based system, in order to prevent system failures. The core should not interfere with system performance and must ensure timely detection of errors. This thesis is an investigation onto how a robust hardware-monitoring module can be efficiently integrated in a target PCI board (with FPGA-based application processing features) which is part of a critical computing system.

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With increasing demand for modern technology in the communication systems, antenna arrays have attracted much interest in the areas of radio broadcasting, space communication, weather forecasting, radar and imaging. Antenna array with controlled low or ultralow sidelobes is of particular importance and it has been an on-going challenge for the antenna design engineers in the past few decades, as it requires a high dynamic range of excitations. Another desired feature provided by an antenna array is the ability to perform electronic beam steering and adaptive interference suppression. These benefits can be achieved with the use of complicated feed network and expensive phase shifters and it can only found in the specialised military systems. Therefore this has motivated the research into the development of a simple and low cost system for the commercial applications. The idea of time modulation was proposed to produce an antenna pattern with controlled low or ultralow sidelobe level, as well as achieving real time electronic beam scanning without the use of phase shifter. However, a fundamental problem of this concept is the generation of undesired harmonics or sidebands as they waste power. This dissertation mainly focuses on the two important characteristics - pattern synthesis and multiple beams scanning of the time modulated antenna array and evaluates its potential application in the communication system. The first main chapter of this research proposes two novel approaches to successfully suppress the sideband radiation and hence improve radiation efficiency. The following part of the study introduces a way of combining the electronic beam scanning with the controlled low or ultralow sidelobes and applies the null steering technique in the time modulated linear array. The final but most important attribute of this thesis is to propose the concept of time redundancy and evaluate the potential feasibility of employing smart antenna technology into the time modulated antenna array for a two-channel communication system, where individual adaptive beamforming can be performed to extract desired signal while suppressing interference from separate sources independently.