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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

A 2.4GHz, Low Power, Fully-Integrated CMOS Frequency Synthesizer for Wireless Communications

Zhang, Benyong 05 1900 (has links)
No description available.

Generating just temperament with ideal rate multiplication /

Moore, Andrew C. January 1991 (has links)
Thesis (M.S.)--Rochester Institute of Technology, 1991. / Typescript. Includes bibliographical references (leaves 59-60).

Optimizing the performance of direct digital frequency synthesizers for low-power wireless communication systems

Betowski, David James, January 2004 (has links) (PDF)
Thesis (M.S. in computer engineering)--Washington State University. / Includes bibliographical references.

Interpolation-based digital quadrature frequency synthesizer

Larson, Ryan John 05 June 2000 (has links)
Traditionally sinusoidal signal generation has been implemented with purely analog circuits such as phase-locked loops. The alternative of using a digital system to perform this signal generation has previously been unattractive due to limitations in clock frequency and size. However, recent advancements in sub-micron fabrication techniques have made the digital alternative tractable. The advantages of a digitally implemented signal frequency synthesizer include finer control of output frequency, reduced frequency drift due to part degradation over time, and faster response time for frequency change. Digital frequency synthesis has been previously realized using the Tierney, Rader, and Gold phase accumulator architecture. This method utilizes a variable-increment digital integrator that is input to a read-only memory. This memory then generates a quantized amplitude value. This thesis presents an alternative method for digital frequency synthesis based on circular interpolation and compares it to the performance of a comparable phase-accumulator structure for varying bit accuracies of phase. The comparison of transistor count and required die-size for each method reveals a lower requirement of both resources in the case of the new circle interpolator. Evaluation of the discrete-time spectral purity of synthesized signals also demonstrates less out of band noise in the new design. Finally, analysis of energy efficiency shows the new design to be generally optimal compared to the reference design. / Graduation date: 2001

A laboratory Fourier Synthesizer using hybrid (analog/digital) techniques

Amerine, Marvin Keith, 1945- January 1976 (has links)
No description available.

Direct digital synthesis by analogue interpolation

McEwan, Alistair January 2004 (has links)
An improvement in efficiency of direct digital frequency synthesis (DDFS) systems is demanded for low power frequency synthesis in wireless communications. Concurrently a reduction in cost is important for disposable, low resolution frequency synthesis in biomedical instrumentation systems. To meet both these needs a new ROM-less architecture is presented here that uses less than half the circuit area of previous state of the art systems and improves the efficiency by operating at up to a tenth of the power consumption. The main contribution presented in this thesis is a novel, efficient method of interpolation for DDFS that uses the nonlinear response of the CMOS differential switch already present in the high speed current steering DAC. The nonlinear response provides a smooth transition between the conventional, quantised DAC output. This interpolation may be performed with the conventionally discarded phase bits leading to highly compact and efficient DDFS architectures for application in instrumentation and communications systems. DDFS systems typically consist of a large overflowing accumulator to generate the phase, a ROM lookup table to convert the phase to amplitude and a DAC to perform the digital to analogue conversion. Approximations are often used to reduce the size of the ROM, however the most efficient DDFS systems remove the ROM completely and calculate the phase to amplitude conversion directly or store the conversion in a non-linear DAC. State of the art, high speed CMOS DACs consisting of thermometer decoded arrays of current steering cells are often used to reduce non-ideal effects that cause unwanted transients leading to a degradation in spectral purity (SFDR). A novel ROM-less technique is introduced here that uses the non-linear response of a current cell consisting of an ideal current source and differential current switch to interpolate between the output levels of a non-linear DAC. Using this technique two architectures are developed. A compact architecture using only four or six current cells suitable for instrumentation applications and a thermometer decoded architecture using 64 current cells for communications applications that require better spectral purity. The compact architecture is 100% efficient as all the bias current is used to form the output. The only additional component is a small linear phase DAC. One compact system with a nonlinear DAC of four current cells achieved an SFDR of -40dBc up to output frequencies of 1MHz for dielectrophoresis consumed only 5μW/MHz and a second compact system with a six cell nonlinear DAC for electrical impedance spectroscopy, achieved an SFDR of -48dBc for output frequencies up to 1MHz and consumed only 8μW/MHz. As an extension to improve the SFDR a segmented system with 64 current cells was developed. The larger number of current cells required the use of a modified thermometer decoder that had the added benefit of improving the spectral purity by linearising the response of each cell. The total active area was 0.6mm<sup>2</sup>, less than half of state of the art ROM-less DDFS systems that include a DAC. Although measurement results of the 64 cell system were disappointing, simulations suggest that these problems may be solved in a future chip that should be able to achieve -70dBc SFDR at 100MHz. Despite the loss in performance from simulation to measurement, the measured 64 cell system still meets the spectral purity requirements of UMTS and Bluetooth, -60dBc SFDR.

Near field microwave imaging techniques for embedded object detection and shape reconstruction

Tantong, Somsak. January 2007 (has links)
Thesis (M.S.)--University of Missouri-Columbia, 2007. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on January 11, 2008) Includes bibliographical references.

0.18um phase/frequency detector and charge pump design for digital video broadcasting for handheld's phase-locked-loop systems

Al Sabbagh, Mhd Zaher , January 2008 (has links)
Thesis (M.S.)--Ohio State University, 2008. / Title from first page of PDF file. Non-Latin script record Includes bibliographical references (p. 35-36).

A 5 GHz digitally controlled synthesizer in 90nm CMOS

Hamon, Bill. January 2009 (has links) (PDF)
Thesis (M.S. in electrical engineering)--Washington State University, May 2009. / Title from PDF title page (viewed on July 15, 2009). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 83-88).

Phase locked loop analysis and design

Ratcliff, Marcus. Dai, Foster, January 2008 (has links)
Thesis--Auburn University, 2008. / Abstract. Includes bibliographical references (p. 49-50).

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