Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 152-157).

Αντικείμενο της παρούσης διπλωματικής εργασίας είναι ο σχεδιασμός ενός συνθέτη συχνοτήτων για MB-OFDM (Multiband Orthogonal Frequency-Division Multiplexing) UWB εφαρμογές. Ο συνθέτης συχνοτήτων αποτελεί εξέχουσας σημασίας δομικό στοιχείο των RF πομποδεκτών αφού είναι υπεύθυνος για την παραγωγή του (LO oscillator) σήματος που οδηγεί τον downconverter και τον upconverter στο μονοπάτι του δέκτη και του πομπού αντίστοιχα. Μελετήθηκαν οι δομές, οι κυριότερες τοπολογίες και τα χαρακτηριστικά ενός τυπικού συνθέτη συχνοτήτων καθώς και τα κύρια εξαρτήματα που το απαρτίζουν. Αφού μελετήσαμε το βασικό και το εναλλακτικό σχέδιο συχνοτήτων όπως παρουσιάζεται από το MB-OFDM πρότυπο προτείναμε την κατάλληλη τοπολογία η οποία και διαφέρει από αυτή των τυπικών συνθετών συχνοτήτων που χρησιμοποιούνται ευρέως στα ασύρματα συστήματα τηλεπικοινωνιών λόγω των υψηλών απαιτήσεων της UWΒ τεχνολογίας. Η επιλογή των εξαρτημάτων που απαρτίζουν τον συνθέτη συχνοτήτων έγινε με βάση την ελαχιστοποίηση του θορύβου φάσης και της κατανάλωσης ισχύος, της εξάλειψης ανεπιθύμητων σημάτων στην έξοδό του, τα οποία μπορούν να δημιουργήσουν παρεμβολές σε άλλα τηλεπικοινωνιακά συστήματα καθώς και την επίτευξη μικρού χρόνου αποκατάστασης που απαιτεί ένας τέτοιος συνθέτης. Προτείνεται και εξομοιώθηκε λοιπόν συνθέτης συχνοτήτων με περιοχή λειτουργίας του από 3.1 έως 10.6 GHz με βήμα συχνότητας 528 MHz όπως αυτή ορίζεται από το πρότυπο 802.15.3 που αναφέρεται στην UWB τεχνολογία. Από τα αποτελέσματα της εξομοίωσης προκύπτει ότι επιτυγχάνεται χαμηλός θόρυβος φάσης, μικρός χρόνος αποκατάστασης και μικρή ισχύς των ανεπιθύμητων σημάτων, αποτελέσματα που συνάδουν με τις απαιτήσεις της UWB τεχνολογίας. Τέλος προτείνεται και υλοποιείται η πλακέτα του βρόχου κλειδωμένης φάσης ο οποίος και αποτελεί το βασικό δομικό στοιχείο του συνθέτη συχνοτήτων. / The subject of the present essay is the design of a frequency synthesizer for MB-OFDM (Multiband Orthogonal Frequency-Division Multiplexing) UWB applications. The frequency synthesizer is a structural part of foremost importance at the RF transceivers, as it is responsible for the production of the signal (LO oscillator) that leads the downconverter and the upconverter at the path of the receiver and the transmitter correspondingly. Structures, principal topologies and a typical’s frequency synthesizer characteristics have been studied, as well as the main components that compose it. After having studied the current and the alternate frequency plan –as presented by MB-OFDM standard-, we proposed the proper topology, which is different from the one for the typical frequency synthesizers, that are widely used at the RF communication systems, due to UWB technology’s high specifications. The choice of the components that compose the frequency synthesizer is based on the minimization of the phase noise and the power consumption, on the reduction of spurious signals during its entrance, which can create interferences to other communicational systems, as well as on the accomplishment of a short settling time, which a synthesizer of this kind demands. So, a frequency synthesizer with a frequency range from 3.1 to 10.6 GHz, with a frequency step of 528 MHz -as it is defined from the standard 802.15.3 that is referred at UWB technology-, has been proposed and simulated. From the results of the simulation, it emerges that a low phase noise is accomplished, a short settling time and a low power of spurious signals, results that add up to UWB technology’s specifications. Finally, the PCB (printed circuit board) of the phase locked loop - which consists the basic structural part of the frequency synthesizer - has been proposed and implemented.

Στην παρούσα Διπλωματική Εργασία μελετάται η αρχιτεκτονική και τα χαρακτηριστικά ενός νέου συνθέτη συχνοτήτων (Frequency Synthesizer) που βασίζεται στην τεχνική του βρόχου κλειδωμένης φάσης (Phase-Locked Loop). Η νέα αρχιτεκτονική ξεπερνά την δυσκολία του απλού συνθέτη συχνοτήτων να έχει ταυτόχρονα μικρό βήμα συχνότητας και μικρό χρόνο κλειδώματος, ενώ ταυτόχρονα διατηρεί και επαυξάνει την δυνατότητα των απλών συνθετών να απορρίπτουν τον θόρυβο φάσης, δίνοντας έτσι πολύ καλή ποιότητα σήματος εξόδου. Τα χαρακτηριστικά αυτά καθιστούν τον νέο συνθέτη πολύ ανταγωνιστικό. / This Diploma Thesis studies the architecture and the characteristics of a new Frequency Synthesizer which based on the Phase-Locked Loop technique. This new architecture overcomes the difficulty of the simple frequency synthesizer to have simultaneously small frequency step and small locking time, while maintains and enhances the possibility to reject phase noise. This concludes to the high quality of the output signal. The above characteristics make the new synthesizer very competitive.

Σκοπός αυτής της διπλωματικής εργασίας είναι η σχεδίαση και υλοποίηση συνθέτη συχνοτήτων διπλού βρόχου σε συχνότητες 3-6 GHz για ασύρματες εφαρμογές UWB και HiperLAN2. Ο συνθέτης συχνοτήτων σχεδιάστηκε με διακριτά στοιχεία, χρησιμοποιώντας την αρχιτεκτονική του βρόχου κλειδωμένης φάσης (PLL) και λειτουργεί με 2 τρόπους, είτε παράγοντας σήματα συχνότητας από 3168 MHz έως 6336 MHz με βήμα συχνότητας 528 MHz, είτε παράγοντας σήματα συχνότητας από 4800 MHz έως 5000 MHz με βήμα συχνότητας 10 MHz. Παρά το γεγονός ότι η αρχιτεκτονική διπλού βρόχου έχει αντικατασταθεί από την αρχιτεκτονική fractional-N για λόγους κατανάλωσης και κόστους, πλεονεκτεί σε εφαρμογές ασύρματων δικτύων με αυστηρές απαιτήσεις ως προς την ακρίβεια της παραγόμενης συχνότητας και το θόρυβο φάσης. Η απλή αρχιτεκτονική integer-N δεν είναι επαρκής για την εκπλήρωση των απαιτήσεων σε μεγάλη ευκρίνεια και μικρό θόρυβο φάσης, λόγω του περιορισμένου εύρους ζώνης του βρόχου και του μεγάλου λόγου διαίρεσης Ν του διαιρέτη συχνοτήτων του βρόχου. Με την αρχιτεκτονική διπλού βρόχου χρησιμοποιούμε δυο βρόχους για να αμβλύνουμε την αντίθεση μεταξύ των παραπάνω παραγόντων, οι οποίοι καθορίζουν τη συμπεριφορά και την απόδοση του συνθέτη συχνοτήτων. Με τη χρήση διακριτών στοιχείων για την υλοποίηση των δυο βρόχων αποσκοπούμε σε καλύτερη συμπεριφορά του συστήματος ως προς το θόρυβο φάσης, καθώς και σε πιο ευέλικτο σχεδιασμό, που δίνει τη δυνατότητα μείωσης της ισχύος των ανεπιθύμητων συνιστωσών του σήματος αναφοράς στην έξοδο του συστήματος. / The purpose of this diploma thesis is the design and implementation of a dual loop frequency synthesizer, operating at frequencies ranging from 3 to 6 GHz, for wireless network applications, using UWB and HiperLAN2 standards. The frequency synthesizer’s design was based on dual loop synthesizer architecture and the use of modular components. The designed frequency synthesizer is able to function in 2 modes, by either producing signals in the frequency range of 3168 MHz - 6336 MHz with 528 MHz resolution, or signals in the frequency range of 4800 MHz - 5000 MHz with 10 MHz resolution. Although the dual loop architecture has long been replaced by the fractional-N architecture due to increased cost and power consumption, it is more suitable in wireless network applications demanding high precision in frequency synthesis and low phase noise. The integer-N architecture fails to satisfy these demands, due to the limited loop bandwidth and the large division ratio Ν of the loop’s frequency divider. The dual loop architecture uses two loops in order to alleviate the opposing demands in high frequency synthesis accuracy and low phase noise, which determine the behavior and performance of the frequency synthesizer. The use of modular components aims at better phase noise performance, as well as a more flexible design, thus resulting in a more efficient power dissipation of the spurious components of the reference signal at the synthesizer output.

Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1976 / Includes bibliographical references. / M.S. / M.S. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

A fully integrated, fast-locking fractional-N frequency synthesizer is proposed and demonstrated in this work. In this design, to eliminate the need for large, inaccurate capacitors and resistors in a loop filter, an analog continuous-time loop filter whose performance is sensitive to process and temperature variations and aging has been replaced with a programmable digital Finite Impulse Response (FIR) filter. In addition, using the adaptive loop gain control proportional to the frequency difference, the frequency-locking time has been reduced. Also, the phase noise and spurs have been reduced by a Multi-stAge noise SHaping (MASH) controlled Fractional Frequency Detector (FFD) that generates a digital output corresponding directly to the frequency difference. The proposed frequency synthesizer provides many benefits in terms of high integration ability, technological robustness, fast locking time, low noise level, and multimode flexibility. To prove performance of the proposed frequency synthesizer, the frequency synthesizers analysis, design, and simulation have been carried out at both the system and the circuit levels. Then, the performance was also verified after fabrication and packaging.

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs. In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.

The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.

In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.

Recent research focuses on expanding the use of RF/Microwave circuits and systems to include multi-disciplinary applications. One example is the detection of the dielectric properties of chemicals and bio-chemicals at microwave frequencies, which is useful for pharmaceutical applications, food and drug safety, medical diagnosis and material characterization. Dielectric spectroscopy is also quite relevant to detect the frequency dispersive characteristics of materials over a wide frequency range for more accurate detection. In this dissertation, on-chip and on-board solutions for microwave chemical sensing are proposed. An example of an on-chip dielectric detection technique for chemical sensing is presented. An on-chip sensing capacitor, whose capacitance changes when exposed to material under test (MUT), is a part of an LC voltage-controlled oscillator (VCO). The VCO is embedded inside a frequency synthesizer to convert the change in the free runing frequency frequency of the VCO into a change of its input voltage. The system is implemented using 90 nm CMOS technology and the permittivities of MUTs are evaluated using a unique detection procedure in the 7-9 GHz frequency range with an accuracy of 3.7% in an area of 2.5 × 2.5 mm^2 with a power consumption of 16.5 mW. The system is also used for binary mixture detection with a fractional volume accuracy of 1-2%. An on-board miniaturized dielectric spectroscopy system for permittivity detec- tion is also presented. The sensor is based on the detection of the phase difference be- tween the input and output signals of cascaded broadband True-Time-Delay (TTD) cells. The sensing capacitor exposed to MUTs is a part of the TTD cell. The change of the permittivity results in a change of the phase of the microwave signal passing through the TTD cell. The system is fabricated on Rogers Duroid substrates with a total area of 8 × 7.2 cm2. The permittivities of MUTs are detected in the 1-8 GHz frequency range with a detection accuracy of 2%. Also, the sensor is used to extract the fractional volumes of mixtures with accuracy down to 1%. Additionally, multi-band and multi-standard communication systems motivate the trend to develop broadband front-ends covering all the standards for low cost and reduced chip area. Broadband amplifiers are key building blocks in wideband front-ends. A broadband resistive feedback low-noise amplifier (LNA) is presented using a composite cross-coupled CMOS pair for a higher gain and reduced noise figure. The LNA is implemented using 90 nm CMOS technology consuming 18 mW in an area of 0.06 mm2. The LNA shows a gain of 21 dB in the 2-2300 MHz frequency range, a minimum noise figure of 1.4 dB with an IIP3 of -1.5 dBm. Also, a four-stage distributed amplifier is presented providing bandwidth extension with 1-dB flat gain response up to 16 GHz. The flat extended bandwidth is provided using coupled inductors in the gate line with series peaking inductors in the cascode gain stages. The amplifier is fabricated using 180 nm CMOS technology in an area of 1.19 mm2 achieving a power gain of 10 dB, return losses better than 16 dB, noise figure of 3.6-4.9 dB and IIP3 of 0 dBm with 21 mW power consumption. All the implemented circuits and systems in this dissertation are validated, demonstrated and published in several IEEE Journals and Conferences.