No description available.

No description available.

Approved for public release; distribution is unlimited / The space environment has unique hazards that force electronic systems designers to use different techniques to build their systems. Radiation can cause Single Event Upsets (SEUs) which can cause state changes in satellite systems. Mitigation techniques have been developed to either prevent or recover from these upsets when they occur. At the same time, modifying on-orbit systems is difficult in a hardwired electronic system. Finding an alternative to either working around a mistake or having to keep the same generation of technology for years is important to the space community. Newer programmable logic devices such as Field Programmable Gate Arrays (FPGAs) allow for emulation of complex logic circuits, such as microprocessors. FPGAs can be repro-grammed as necessary, to account for errors in design, or upgrades in software logic circuits. In an effort to provide one solution for both of these issues, this research was undertaken. The Configurable Fault Tolerant Processor (CFTP) emulates three identical processors, using Triple Modular Redundancy (TMR) to mitigate SEUs on a radiation tolerant FPGA. With the reconfigurable capabilities of FPGA technology, as newer processors can be emulated, these new configurations can be uploaded to the satellite as software code, thereby actually upgrading the processor in flight. This research used a 16-bit Reduced Instruction Set Computer (RISC) processor as its cores. This thesis describes how the Harvard architecture of the processor is interfaced with the Von Neumann architecture of the memory. It also develops the process by which errors are detected and corrected, as well as recorded. The end result is a design simulation ready for implementation on an FPGA. / Lieutenant, United States Navy

Thesis (Ph.D.)--University of Delaware, 2006. / Principal faculty advisor: Dennis W. Prather, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

Digital Signal Processors (DSPs) have been an important component of all signal processing systems for over two decades now. Some of the obvious advantages of digital signal processing are the flexibility to make specific changes in the processing functions through hardware or software programming, faster processing speeds of the DSPs, cheaper storage, and retrieval of digital information and lower sensitivity to electrical noise. The explosive growth of wireless and signal processing applications has resulted in an increasing demand for such systems with low cost, low power consumption, and small form factors. With high--level of integration to single--chip systems, power consumption becomes a very important concern to be addressed. Intermediate--Frequency (IF) band signal processing requires the use of an array of DSPs, operating in parallel, to meet the speed requirements. This is a power intensive approach and makes use of certain communication schemes impractical in applications where power budget is limited. The front--end ADC and back--end DAC converters required in these systems become expensive when the signal is of wideband nature and a greater resolution is required. We present techniques to use floating--gate devices to implement signal processing systems in the analog domain in a power efficient and cost effective manner. Use of floating--gate devices mitigates key limitations in analog signal processing such as the lack of flexibility to specific changes in processing functions and the lack of programmability. This will impact the way a variety of signal processing systems are designed currently. It also enables array signal processing to be done in an area efficient manner. As will be shown through sample applications, this methodology promises to replace expensive wideband ADC and DAC converters with relatively easy to implement baseband data converters and an array of power intensive high speed DSPs with baseband DSPs. This approach is especially beneficial for portable systems where a lot of applications are running from a single battery.

The traditional displayer ¡V CRT has already been substituted by liquid crystal displayer (LCD).The a-Si TFT is used to be a switch, while the size of the displayer increases, the require of the performance and quality of TFTs is more and more better. Therefore, it is very important subject to study the stability and to improve the performance of a-Si TFTs. In this study, it simulated the process of the degradation on the TFTs by changing the sizes of TFTs and bias modes to find to stability mechanism of the TFTs. It can be known that under AC stress the degradation depends on the channel length, longer channel length with less degradation. In order to improve the traditional dual-gate structure TFTs, it had made dual-gate TFTs with ITO back-gate, the process of the new structure TFTs are fully compatible with the conventional BCE TFT fabrication process. With dual-channel conduction, the dual-gate TFTs exhibit higher on current and lower photo leakage current performance than the conventional inverted staggered TFTs In this study it also use the dual-gate structure to investigate how the back-channel influence the front-channel conduction. Apply DC bias on the back-gate to from defects at the interface of the active layer and passvation layer, it is found that after stress the on-current show almost the same quantities, and the photo leakage current is obvious decreased.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2003. / Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 117). Also available online.

Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive applications. These applications use advanced algorithms more sophisticated than ever before. The high design complexity along with fast development process challenges the traditional FPGA design methodology using hardware description languages. High-level synthesis accelerates design implementation by raising the level of design abstraction beyond register transfer level. This dissertation work develops a highly energy-efficient FPGA high-level synthesis tool, ArchSyn, using an application-specific coarse-grain architecture as an intermediate synthesis step. ArchSyn provides rapid and energy-efficient compilation of dataflow graphs (DFGs) on FPGAs by scheduling the dataflow operations on an array of directly connected simple configurable processing elements (CPEs). Each CPE in the array performs primitive compute operations according to a small local sequencer at each cycle. Data are communicated via multi-hop routing within the direct interconnect network. The scheduler schedules each compute operation of the DFG obtained from the high-level design to execute on a particular hardware CPE at a particular cycle. It also determines the communication schedule of the intermediate data among the producing and consuming CPEs, optionally buffering them with distributed memory along the path. As such, the lengthy process of synthesizing a full custom hardware design on FPGA is reduced to a scheduling and mapping process. By restricting the fine-grain programmability into a coarse grain processor network scheduling problem, the compilation time can be improved substantially, thereby improving the overall productivity of the designer. Furthermore, taking advantage of the programmability of FPGAs, the effect of the array interconnect architecture on the energy-efficiency of the resulting system is studied. By altering the array configuration, the data communication scheme among the CPEs must also be changed. This has a net effect on both the energy consumption spent on data movement as well as on the overall compute performance. It is shown that by using array topology that is customized to the input DFG, up to 28% improvement in energy-efficiency could be achieved. An exploratory framework based on a genetic algorithm was developed that allows us to obtain such application-specific connection network. Such degree of customization is possible only with the programmability of FPGAs. Moreover, such topology adaptation can be achieved rapidly as only routings between a fixed set of pre-placed CPEs are required. Implementations using ArchSyn and an existing FPGA compilation tool xPilot were compared. ArchSyn gave a 2X better energy consumption and a 11X better energy-delay product for computation with very regular and simple data dependency. For computation with irregular data dependency, the energy consumption and energy-delay product improvement was 9.6X and 199X. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Not available / text

Thesis (Ph. D.)--University of Hawaii at Manoa, 1994. / Includes bibliographical references (leaves 185-186). / Microfiche. / xviii, 186 leaves, bound ill. 29 cm