The traditional displayer ¡V CRT has already been substituted by liquid crystal displayer (LCD).The a-Si TFT is used to be a switch, while the size of the displayer increases, the require of the performance and quality of TFTs is more and more better. Therefore, it is very important subject to study the stability and to improve the performance of a-Si TFTs. In this study, it simulated the process of the degradation on the TFTs by changing the sizes of TFTs and bias modes to find to stability mechanism of the TFTs. It can be known that under AC stress the degradation depends on the channel length, longer channel length with less degradation. In order to improve the traditional dual-gate structure TFTs, it had made dual-gate TFTs with ITO back-gate, the process of the new structure TFTs are fully compatible with the conventional BCE TFT fabrication process. With dual-channel conduction, the dual-gate TFTs exhibit higher on current and lower photo leakage current performance than the conventional inverted staggered TFTs In this study it also use the dual-gate structure to investigate how the back-channel influence the front-channel conduction. Apply DC bias on the back-gate to from defects at the interface of the active layer and passvation layer, it is found that after stress the on-current show almost the same quantities, and the photo leakage current is obvious decreased.

The traditional displayer ¡V CRT has already been substituted by liquid crystal displayer (LCD).The a-Si TFT is used to be a switch, while the size of the displayer increases, the require of the performance and quality of TFTs is more and more better. Therefore, it is very important subject to study the stability and to improve the performance of a-Si TFTs. In this thesis, we fabricate another new structure (asymmetry dual-gate TFTs).For asymmetry dual-gate TFTs, the ITO back gate is extended to the middle of the channel and only covered on the drain contact. The new structure has the advantages of dual-gate TFTs. With dual-channel conduction, it exhibit higher Ion and lower photo leakage current performance than the conventional inverted staggered TFTs. In addition, we use the asymmetry dual-gate structure to investigate how the parasitic capacitance influences the feed-through voltage by C-V measurement. We also to investigate the influences of electrical characteristics with the ITO back gate whether or not overlap the source contact. The asymmetry in on current with source-drain swapping can be attributed to the difference in the ITO back gate whether overlaps the source contact. Finally, it simulated the process of the degradation on the TFTs to find the stability mechanism of the TFTs.

A new multiple-gate transistor, the SOI MOS-JFET, is presented. This device combines the MOS field effect and junction field effect within one transistor body. Measured I-V characteristics are provided to illustrate typical modes of operation and the functionality associated with each gate. Two-dimensional simulations of the device?s cross-section will be presented to illustrate various conduction modes under different bias conditions. Test results indicate the MOS-JFET is well suited for both high-voltage and low-voltage circuit demands for systems-on-a-chip applications on SOI technology. Analog building-block circuits based the MOS-JFET are also presented.

No description available.

Interactive handheld electronic displays use hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) as a backplane and a Touch Screen Panel (TSP) on top as an input device. The low mobility and instability of a-Si:H TFT threshold voltage are major two issues for driving constant current as required for Active Matrix Organic Light Emitting Ddiode (AMOLED) displays. Low mobility is compensated by increasing transistor width or resorting to more expensive material TFTs. On the other hand, the ever increasing threshold voltage shift degrades the drain current under electrical operation causing OLED display to dim. Mutual capacitive TSP, the current cell phone standard, requires two layers of metals and a dielectric to be put in front of the display, further dimming the device and adding to visual noise due to sun reflection, not to mention increased integration cost and decreased yield. This thesis focuses on the aforementioned technological hurdles of a handheld electronic display by proposing a dual-gate TFT used as an OLED current driving TFT and a novel phase response readout scheme that can be applied to a one metal track TSP. Our dual-gate TFT has shown on average 20% increase in drive current over a single gate TFT fabricated in the same batch, attributed to the aid of a top channel to the convention bottom channel TFT. Furthermore the dual gate TFT shows three times the Poole-Frenkel current than the single gate TFT attributed to the increase in gate to drain overlap. The dual-gate TFT shows a 50% improvement in threshold voltage shift over a single gate TFT at room temperature, but only ~8% improvement under 75ºC. This is an important observation as it shows an accelerated threshold voltage shift in the dual-gate. This difference in the rate of threshold voltage change under varying temperature is attributed to the difference in interface states, supporting Libsch and Kanicki’s multi-level temperature dependant dielectric trapping model. The phase response TSP readout scheme requires IC only on one side of the display. Cadence Spectre simulation results showed that both touch occurrence and touch position can be obtained using only one metal layer.

Interactive handheld electronic displays use hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) as a backplane and a Touch Screen Panel (TSP) on top as an input device. The low mobility and instability of a-Si:H TFT threshold voltage are major two issues for driving constant current as required for Active Matrix Organic Light Emitting Ddiode (AMOLED) displays. Low mobility is compensated by increasing transistor width or resorting to more expensive material TFTs. On the other hand, the ever increasing threshold voltage shift degrades the drain current under electrical operation causing OLED display to dim. Mutual capacitive TSP, the current cell phone standard, requires two layers of metals and a dielectric to be put in front of the display, further dimming the device and adding to visual noise due to sun reflection, not to mention increased integration cost and decreased yield. This thesis focuses on the aforementioned technological hurdles of a handheld electronic display by proposing a dual-gate TFT used as an OLED current driving TFT and a novel phase response readout scheme that can be applied to a one metal track TSP. Our dual-gate TFT has shown on average 20% increase in drive current over a single gate TFT fabricated in the same batch, attributed to the aid of a top channel to the convention bottom channel TFT. Furthermore the dual gate TFT shows three times the Poole-Frenkel current than the single gate TFT attributed to the increase in gate to drain overlap. The dual-gate TFT shows a 50% improvement in threshold voltage shift over a single gate TFT at room temperature, but only ~8% improvement under 75ºC. This is an important observation as it shows an accelerated threshold voltage shift in the dual-gate. This difference in the rate of threshold voltage change under varying temperature is attributed to the difference in interface states, supporting Libsch and Kanicki’s multi-level temperature dependant dielectric trapping model. The phase response TSP readout scheme requires IC only on one side of the display. Cadence Spectre simulation results showed that both touch occurrence and touch position can be obtained using only one metal layer.

No description available.

Dans le contexte des transports plus électriques, les parties mécaniques tendent à être remplacées par leurs équivalents électriques plus petits. Ainsi, le composant lui-même doit supporter un environnement plus sévère et de lourdes contraintes (haute tension, haute température). Les composants silicium deviennent alors inappropriés. Depuis la commercialisation des premières diodes Schottky en 2001, le carbure de silicium est le matériau reconnu mondialement pour la fabrication de dispositifs haute tension avec une forte intégration. Sa large bande d'énergie interdite et son fort champ électrique critique permettent la conception de transistors à effet de champ avec jonction (JFET) pour les hautes tensions ainsi que les diodes associées. Les structures étudiées dépendent de nombreux paramètres, et doivent ainsi être optimisées. L'influence d'un paramètre ne pouvant être isolée, des méthodes mathématiques ont été appelées pour trouver la valeur optimale. Ceci a conduit à la mise en place d'un critère d'optimisation. Ainsi, les deux grands types de structures de JFET verticaux ont pu être analysés finement. D'une part, la recherche d'une structure atteignant les tensions les plus élevées possible a conduit à l'élaboration d'un procédé de fabrication complexe. D'autre part, un souci de simplification et de stabilisation des procédés de fabrication a permis le développement d'un composant plus simple, mais avec une limite en tension un peu plus modeste. / In the context of more electrical transports, mechanical devices tend to be replaced by their smaller electrical counterparts. However the device itself must support harsher environment and electrical constraints (high voltage, high temperature) thus making existing silicon devices inappropriate. Since the first Schottky diode commercialization in 2001, Silicon Carbide (SiC) is the favorite candidate for the fabrication of devices able to sustain high voltage with a high integration level. Thanks to its wide band gap energy and its high critical field, 4H-SiC allows the design of high voltage Junction Field Effect Transistor (JFET) with its antiparallel diode. Studied structures depends of many parameters, that need to be optimized. Since the influence of the variation of each parameter could not be isolated, we tried to find mathematical methods to emphase optimal values leading to set an optimization criterion. Thus, two main kinds of JFET structure were finely analyzed. In one hand, the aim of the structure that can sustain a voltage as high as possible leads to a complex fabrication process. In the other hand, the care of a simplification and a stabilization of manufacturing process leads to the design of simpler device, but with a bit less sustain capabilities.