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The development of digital technology permits the storage and processing of binary data at high rates, with high precision and density. Therefore, over the past few decades, Moore's law has pushed the development of scaling semiconductor devices for computing hardware. Although the current downward scaling trend has reached its scaling limits, a new "More-than-Moore" (MtM) trend has been emphasized as a diversified function of data collection, storage units, and processing devices. The function diversification defined in MtM can be viewed as an alternative form of "scaling down" for electronic systems, as it incorporates non-computing functions into digital ones, allowing digital devices to interact directly with the environment around them. Two-dimensional (2D) materials display promising potential for combining optical sensing and data storage with broadband photoresponse, outstanding photoresponsivity, rapid switching speed, multi-bit data storage, and high energy efficiency. In this work, in-solution 2D materials flakes (Hafnium Diselenide (HfSe2) and Germanium Selenide (GeSe) have been studied as a charge-trapping layer in non-volatile memory through the seamless fabrication process. Furthermore, the behavior of fabricated non-volatile memories under light illumination has been investigated towards in-memory light sensing. Atomic Force Microscopy, RAMAN spectroscopy, and X-ray Diffraction Spectroscopy characterized the charge-trapping materials. The electrical characterization of Metal Oxide Semiconductor (MOS) Capacitor memory revealed a memory window of 4V for the HfSe2 device under ±10V biasing. Intriguingly, the GeSe device exhibited an extraordinarily wide memory window of 11V under the same electrical biasing. Furthermore, the memory endurance for both materials as charge trapping layer (CTL) exceeds the standard threshold of electrical programming and erasing cycles. The accelerated retention test at different temperatures showed the memory device's stability and reliability for both materials. Under light stimuli with electrical readout voltage, the MOS memory exhibited wavelength and intensity-responsive behavior. The MOS memory of HfSe2 has demonstrated remarkable capabilities in storing the detected light signal, while also exhibiting a noteworthy increase in the memory window of approximately 1.8 V when subjected to a laser wavelength of 405 nm. Meanwhile, the GeSe device's CV measurement revealed a similar trend with the greatest memory window enhancements occurring in relation to 465 nm laser wavelength. Under ±6 V biasing in the absence of light, the memory window was found to be 8.3 V. However, following exposure to a 465 nm laser, this value increased significantly to 9.9 V, representing an increment of 1.6 V. In addition, both devices exhibited distinct sensing of various light intensities and an enhanced memory window as a result of the observable Vt shift caused by altering the levels of illumination. This memory enhancement suggests that photoexcited carriers in the CTL layer were responsible for the optical memory behavior. The 2D materials as CTL pave the way for a reconfigurable optical memory with multilevel optical data storage capacity. This research represents a significant step towards the development of a new generation of memory devices that can store and retrieve data using light signals.

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.

No description available.

Interactive handheld electronic displays use hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) as a backplane and a Touch Screen Panel (TSP) on top as an input device. The low mobility and instability of a-Si:H TFT threshold voltage are major two issues for driving constant current as required for Active Matrix Organic Light Emitting Ddiode (AMOLED) displays. Low mobility is compensated by increasing transistor width or resorting to more expensive material TFTs. On the other hand, the ever increasing threshold voltage shift degrades the drain current under electrical operation causing OLED display to dim. Mutual capacitive TSP, the current cell phone standard, requires two layers of metals and a dielectric to be put in front of the display, further dimming the device and adding to visual noise due to sun reflection, not to mention increased integration cost and decreased yield. This thesis focuses on the aforementioned technological hurdles of a handheld electronic display by proposing a dual-gate TFT used as an OLED current driving TFT and a novel phase response readout scheme that can be applied to a one metal track TSP. Our dual-gate TFT has shown on average 20% increase in drive current over a single gate TFT fabricated in the same batch, attributed to the aid of a top channel to the convention bottom channel TFT. Furthermore the dual gate TFT shows three times the Poole-Frenkel current than the single gate TFT attributed to the increase in gate to drain overlap. The dual-gate TFT shows a 50% improvement in threshold voltage shift over a single gate TFT at room temperature, but only ~8% improvement under 75ºC. This is an important observation as it shows an accelerated threshold voltage shift in the dual-gate. This difference in the rate of threshold voltage change under varying temperature is attributed to the difference in interface states, supporting Libsch and Kanicki’s multi-level temperature dependant dielectric trapping model. The phase response TSP readout scheme requires IC only on one side of the display. Cadence Spectre simulation results showed that both touch occurrence and touch position can be obtained using only one metal layer.

Interactive handheld electronic displays use hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) as a backplane and a Touch Screen Panel (TSP) on top as an input device. The low mobility and instability of a-Si:H TFT threshold voltage are major two issues for driving constant current as required for Active Matrix Organic Light Emitting Ddiode (AMOLED) displays. Low mobility is compensated by increasing transistor width or resorting to more expensive material TFTs. On the other hand, the ever increasing threshold voltage shift degrades the drain current under electrical operation causing OLED display to dim. Mutual capacitive TSP, the current cell phone standard, requires two layers of metals and a dielectric to be put in front of the display, further dimming the device and adding to visual noise due to sun reflection, not to mention increased integration cost and decreased yield. This thesis focuses on the aforementioned technological hurdles of a handheld electronic display by proposing a dual-gate TFT used as an OLED current driving TFT and a novel phase response readout scheme that can be applied to a one metal track TSP. Our dual-gate TFT has shown on average 20% increase in drive current over a single gate TFT fabricated in the same batch, attributed to the aid of a top channel to the convention bottom channel TFT. Furthermore the dual gate TFT shows three times the Poole-Frenkel current than the single gate TFT attributed to the increase in gate to drain overlap. The dual-gate TFT shows a 50% improvement in threshold voltage shift over a single gate TFT at room temperature, but only ~8% improvement under 75ºC. This is an important observation as it shows an accelerated threshold voltage shift in the dual-gate. This difference in the rate of threshold voltage change under varying temperature is attributed to the difference in interface states, supporting Libsch and Kanicki’s multi-level temperature dependant dielectric trapping model. The phase response TSP readout scheme requires IC only on one side of the display. Cadence Spectre simulation results showed that both touch occurrence and touch position can be obtained using only one metal layer.

Hot-wire chemical vapour deposition (HWCVD) is a promising technique that permits polycrystalline silicon films with grain size of nanometers to be obtained at high deposition rates and low substrate temperatures. This material is expected to have better electronic properties than the commonly used amorphous hydrogenated silicon (a-Si:H).In this work, thin-film transistors (TFTs) were fabricated using nanocrystalline hydrogenated silicon film (nc-Si:H), deposited by HWCVD over thermally oxidized silicon wafer. The employed substrate temperature during the deposition process permits inexpensive materials as glasses or plastics to be used for various applications in large-area electronics. The deposition rate was about one order of magnitude higher than in other conventionally employed techniques. The deposited nc-Si:H films show good uniformity and reproducibility. The films consist of vertically grown columnar grains surrounded by amorphous phase. The columnar grains are thinner at the bottom (near the oxide interface) and thicker at the top of the film. Chromium layer was evaporated over the nc-Si:H in order to form drain and source contacts. Using photolithography techniques, two types of samples were fabricated. The first type (simplified) was with the chromium contacts directly deposited over the intrinsic nc-Si:H layer. No dry etching was involved in the fabrication process of this sample. The transistors on the wafer were not electrically separated from each other. Doped n+ layer was incorporated at the drain and source contacts in the second type of samples (complete samples). Dry etching was employed to eliminate the nc-Si:H between the TFTs and to isolate them electrically from each other.The electrical characteristics of both types of nc-Si:H TFTs were similar to a-Si:H based TFTs. Nevertheless, some significant differences were observed in the characteristics of the two types of samples. The increasing of the off-current in the simplified structure was eliminated by the n+ layer in the second type of samples. This led to the improving of the on/off ratio. The n+ layer also eliminated current crowding of the output characteristics. On the other hand, the subthreshold slope, the threshold voltage and the density of states were slightly deteriorated in the samples with incorporated n+ layer. Surface states created by the dry etching could be a possible reason. Other cause could be a bad quality of the nc-Si:H/SiO2 interface. The TFTs with incorporated n+ contact layer and electrically separated on the wafer were used in the further studies of stability and device modelling.The nc-Si:H TFTs were submitted under prolonged positive and negative gate bias stress in order to study their stability. We studied the influence of the stressing time and voltage on the transfer characteristics, threshold voltage, activation energy and density of states. The threshold voltage increased under positive gate bias stress and decreased under negative gate bias stress. After both positive and negative stresses, the threshold voltage recovered its initial values without annealing. This behaviour indicated that temporary charge trapping in the channel/gate insulator interface is the responsible process for the device performance under stress. Measurements of space-charge limited current confirmed that bulk states were not affected by the positive nor by negative stress.Analysis of the activation energy and the density of states gave more detailed information about the physical processes taking place during the stress. Typical drawback of the nc-Si:H films grown by HWCVD with tungsten (W) filament is the bad quality of the bottom, initially grown, interfacial layer. It is normally amorphous and porous. We assume that this property of the nc-Si:H film is determining for charge trapping and the consecutive temporary changes of the TFT's characteristics. On the other hand, the absence of defect-state creation during the gate bias stress demonstrates that the nc-Si:H films did not suffer degradation under the applied stress conditions. The electrical characteristics and the operational regimes of the nc-Si:H TFTs were studied in details in order to obtain the best possible fit using the Spice models for a-Si:H and poly-Si TFTs existing until now. The analysis of the transconductance gm showed behaviour typical for a-Si:H TFTs at low gate voltages. In contrast, at high gate voltages unexpected increasing of gm was observed, as in poly-Si TFTs. Therefore, it was impossible to fit the transfer and output characteristics with the a-Si:H TFT model neither with poly-Si TFT model.We performed numerical simulations using the Silvaco's Atlas simulator of semiconductor devices in order to understand the physical parameters, responsible for the device behaviour. The simulations showed that the reason for this behaviour is the density of acceptor-like states, which situates the properties of nc-Si:H TFTs between the amorphous and the polycrystalline transistors. Taking into account this result, we performed analysis of the concentrations of the free and the trapped carriers in nc-Si:H layer. It was found that nc-Si:H operates in transitional regime between above-threshold and crystalline-like regimes. This transitional regime was predicted earlier, but not experimentally observed until now. Finally, we introduced new equations and three new parameters into the existing a-Si TFTs model in order to account for the transitional regime. The new proposed model permits the shapes of the transconductance, the transfer and the output characteristics to be modelled accurately.

The aim of this work was to find a correlation between the electrical, optical and microstructural properties of thin SiO2 layers containing group IV nanostructures produced by ion beam synthesis. The investigations were focused on two main topics: The electrical properties of Ge- and Si-rich oxide layers were studied in order to check their suitability for non-volatile memory applications. Secondly, photo- and electroluminescence (PL and EL) results of Ge-, Si/C- and Sn-rich SiO2 layers were compared to electrical properties to get a better understanding of the luminescence mechanism.

The aim of this work was to find a correlation between the electrical, optical and microstructural properties of thin SiO2 layers containing group IV nanostructures produced by ion beam synthesis. The investigations were focused on two main topics: The electrical properties of Ge- and Si-rich oxide layers were studied in order to check their suitability for non-volatile memory applications. Secondly, photo- and electroluminescence (PL and EL) results of Ge-, Si/C- and Sn-rich SiO2 layers were compared to electrical properties to get a better understanding of the luminescence mechanism.

This thesis investigated the use of carbon nanotubes as active components in solution processible organic semiconductor devices. We investigated the use of functionalized carbon nanotubes in carbon nanotubes network transistors (CNNFET) and in photoactive composites with conjugated polymers. For CNNFETs, the objective was to obtain detailed understanding of the dependence of transistor characteristics on nanotubes bundle sizes, device geometry and processing. Single walled carbon nanotubes were functionalized by grafting octadecylamine chains onto the tubes, which rendered them dispersible in organic solvents for solution processing. To investigate the dependence of electronic properties of carbon nanotubes networks on bundle size, we developed a centrifugal fractionation protocol that enabled us to obtain nanotube bundles of different diameters. The electronic properties of networks of nanotube bundles deposited from solution were investigated within a CNNFET device configuration. By comparing devices with different degree of bundling we elucidated the dependence of key device parameters (field effect mobility and on/off ratio) on bundle sizes. We further found that, in contrast to traditional inorganic transistors, the electronic properties of the CNNFETs were dominated by the channel rather than contact resistance. Specifically, the apparent mobility of our devices increased with decreasing channel length, suggesting that the charge transport properties of CNNFETs are bulk rather than contacts dominated. This meant that charge traps in the channel of the device had a significant effect on transport properties. We found that charge traps in the channel region introduced by adsorbed oxygen and silanol groups on the SiO2 surface were responsible for the dominant p-type conductance in as-fabricated devices. Based on this understanding, we demonstrated the p-type to n-type conversion of the transistor characteristics of CNNFETs by depositing nanotubes on electron-trapfree dielectric surfaces. Finally, by combining annealing and surface treatment, we fabricated CNNFETs with high n-type mobility of 6cm2/V.s. For polymer composites, the objective was to obtain detailed understanding of the interactions between carbon nanotubes and the conjugated polymer; a prerequisite for using these composites in organic electronic devices. We fabricated well dispersed nanotube/polymer composites by using functionalized carbon nanotubes and studied the effect of nanotubes addition on the photophysical properties of the technologically important conjugated polymer poly(3-hexylthiophene) (P3HT). Measurement of the photoluminescence efficiency of nanotubes/polymer composites showed that addition of 10wt% carbon nanotubes effectively quenched the polymer emission indicating close electronic interactions. This indicated that nanotubes/polymer composites have potential in organic photovoltaic or light-sensing devices. Further analysis of the steady-state photoluminescence spectra revealed that nanotube addition resulted in increased structural disorder in the polymer. The incorporation of structural disorder into the polymer with the addition of even a small amount of carbon nanotubes may be detrimental to charge transport. UV-vis adsorption studies revealed that one-dimensional templating of P3HT chains by nanotubes resulted in a red-shifted feature in the solutionstate optical adsorption spectra of P3HT. This suggested that presence of nanotube surface templates the polymer self-organisation to produce highly ordered coating of P3HT chains around the nanotube. In order to elucidate the nanoscale origin of this phenomenon, we performed detailed STM studies on individual nanotubes adsorbed with P3HT chains. Since carbon nanotubes can be considered as rolled up sheets of graphite, we also performed STM on P3HT chains assembly on graphite for comparison. For P3HT assembly on HOPG, we found that while 2D crystals were observed when P3HT was cast onto HOPG from dilute solution, a thicker and more disordered film resulted when cast from concentrated solutions and subsequent layers were more likely to align normal to an underlying monolayer of P3HT on the HOPG surface. STM studies of nanotube/polymer mixtures revealed that the P3HT chains are adsorbed on nanotubes surface in such a way that the thiophene and hexyl moieties of the polymer associated with the nanotube surface in identical manner to P3HT monolayer depositions on graphite. This resulted in the increased order as inferred from adsorption UV-Vis spectroscopy, where the polymer chains, which are otherwise prone to chain kinks and twists in solution, adopt a planar configuration when adsorbed onto the nanotube surface.