This dissertation proposed two time-domain algorithms for extracting the broadband SPICE-compatible models of high-speed coupled interconnects. The first approach is proposed to synthesized the equivalent models of multi-conductor interconnects by cascading multiple configuration-oriented coupled transmission line (CCTL) units. The second approach focuses on the modeling of differential via based on a broadband macro-£k model with three modules represented by the optimum pole-residue forms. Using a systematic lumped-model extraction technique (SLET), all the pole-residue rational functions can transfer into a corresponding lumped model. The accuracy of the two algorithms is demonstrated both in time- and frequency -domain responses comparison with the direct 3D-FDTD simulation.

This dissertation proposed a novel time-domain algorithm for extracting the broadband SPICE-compatible models of power/ground planes with resonance effect. The time-domain algorithm approach can focus on the modeling of interconnectors and power/ground planes based on a broadband macro model. Every module of the broadband macro model is represented by the optimum pole-residue forms. Using a systematic lumped-model extraction technique, all the optimum pole-residue rational functions can be transferred into a corresponding lumped circuit model. The accuracy of the time-domain algorithms is demonstrated both in time- and frequency-domain responses comparison by the 3D-FDTD simulation and measurement. In addition, these models can be efficiently incorporated into the currently available circuit simulator such as HSpice for the consideration of power/ground bouncing noise with active devices in high-speed circuits.

Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed<br>successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices offered alternative approach, featuring small size<br>and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the<br>Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed<br>signals based systems.<br>Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices<br><div>for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation.</div><div>GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design<br>Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power<br>amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as<br>low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. <br></div><div>These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic<br>Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and<br>digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.<br></div><div><br></div>

Hot-wire chemical vapour deposition (HWCVD) is a promising technique that permits polycrystalline silicon films with grain size of nanometers to be obtained at high deposition rates and low substrate temperatures. This material is expected to have better electronic properties than the commonly used amorphous hydrogenated silicon (a-Si:H).In this work, thin-film transistors (TFTs) were fabricated using nanocrystalline hydrogenated silicon film (nc-Si:H), deposited by HWCVD over thermally oxidized silicon wafer. The employed substrate temperature during the deposition process permits inexpensive materials as glasses or plastics to be used for various applications in large-area electronics. The deposition rate was about one order of magnitude higher than in other conventionally employed techniques. The deposited nc-Si:H films show good uniformity and reproducibility. The films consist of vertically grown columnar grains surrounded by amorphous phase. The columnar grains are thinner at the bottom (near the oxide interface) and thicker at the top of the film. Chromium layer was evaporated over the nc-Si:H in order to form drain and source contacts. Using photolithography techniques, two types of samples were fabricated. The first type (simplified) was with the chromium contacts directly deposited over the intrinsic nc-Si:H layer. No dry etching was involved in the fabrication process of this sample. The transistors on the wafer were not electrically separated from each other. Doped n+ layer was incorporated at the drain and source contacts in the second type of samples (complete samples). Dry etching was employed to eliminate the nc-Si:H between the TFTs and to isolate them electrically from each other.The electrical characteristics of both types of nc-Si:H TFTs were similar to a-Si:H based TFTs. Nevertheless, some significant differences were observed in the characteristics of the two types of samples. The increasing of the off-current in the simplified structure was eliminated by the n+ layer in the second type of samples. This led to the improving of the on/off ratio. The n+ layer also eliminated current crowding of the output characteristics. On the other hand, the subthreshold slope, the threshold voltage and the density of states were slightly deteriorated in the samples with incorporated n+ layer. Surface states created by the dry etching could be a possible reason. Other cause could be a bad quality of the nc-Si:H/SiO2 interface. The TFTs with incorporated n+ contact layer and electrically separated on the wafer were used in the further studies of stability and device modelling.The nc-Si:H TFTs were submitted under prolonged positive and negative gate bias stress in order to study their stability. We studied the influence of the stressing time and voltage on the transfer characteristics, threshold voltage, activation energy and density of states. The threshold voltage increased under positive gate bias stress and decreased under negative gate bias stress. After both positive and negative stresses, the threshold voltage recovered its initial values without annealing. This behaviour indicated that temporary charge trapping in the channel/gate insulator interface is the responsible process for the device performance under stress. Measurements of space-charge limited current confirmed that bulk states were not affected by the positive nor by negative stress.Analysis of the activation energy and the density of states gave more detailed information about the physical processes taking place during the stress. Typical drawback of the nc-Si:H films grown by HWCVD with tungsten (W) filament is the bad quality of the bottom, initially grown, interfacial layer. It is normally amorphous and porous. We assume that this property of the nc-Si:H film is determining for charge trapping and the consecutive temporary changes of the TFT's characteristics. On the other hand, the absence of defect-state creation during the gate bias stress demonstrates that the nc-Si:H films did not suffer degradation under the applied stress conditions. The electrical characteristics and the operational regimes of the nc-Si:H TFTs were studied in details in order to obtain the best possible fit using the Spice models for a-Si:H and poly-Si TFTs existing until now. The analysis of the transconductance gm showed behaviour typical for a-Si:H TFTs at low gate voltages. In contrast, at high gate voltages unexpected increasing of gm was observed, as in poly-Si TFTs. Therefore, it was impossible to fit the transfer and output characteristics with the a-Si:H TFT model neither with poly-Si TFT model.We performed numerical simulations using the Silvaco's Atlas simulator of semiconductor devices in order to understand the physical parameters, responsible for the device behaviour. The simulations showed that the reason for this behaviour is the density of acceptor-like states, which situates the properties of nc-Si:H TFTs between the amorphous and the polycrystalline transistors. Taking into account this result, we performed analysis of the concentrations of the free and the trapped carriers in nc-Si:H layer. It was found that nc-Si:H operates in transitional regime between above-threshold and crystalline-like regimes. This transitional regime was predicted earlier, but not experimentally observed until now. Finally, we introduced new equations and three new parameters into the existing a-Si TFTs model in order to account for the transitional regime. The new proposed model permits the shapes of the transconductance, the transfer and the output characteristics to be modelled accurately.