Nos sistemas computacionais atuais, enquanto é necessário explorar a disponibilidade de múltiplos núcleos, também é obrigatório consumir menos energia. Para acelerar o processo de desenvolvimento de aplicações paralelas e o tornar mais transparente ao programador, Interfaces de Programação Paralela (IPPs) são largamente utilizadas. Entretanto, cada IPP implementa diferentes formas para trocar dados usando regiões compartilhadas da memória. Estas regiões são, geralmente, mais distantes do processador do que regiões privadas da memória e, por consequência, possuem maior tempo de acesso e consumo de energia. Ademais, o sistema de memória dos processadores embarcados é diferente em hierarquia, tamanho, tempo de acesso, consumo de energia, etc., quando comparado aos processadores de propósito geral. Assim, considerando o cenário supracitado, com diferentes IPPs sendo utilizadas em sistemas multicore com diferentes requisitos, neste trabalho será mostrado que cada interface possui comportamento diferente em termos de desempenho, consumo de energia e Energy-Delay Product (EDP), e que este comportamento varia de acordo com a característica da aplicação e o processador utilizado (propósito geral ou embarcado). Por exemplo, Pthreads consome 8% menos energia que o melhor caso de OpenMP; 12% menos que MPI-1; e 8% menos que MPI-2, considerando todos os benchmarks no processador Intel Core i7 (propósito geral). Em contrapartida, no processador ARM Cortex-A9 (sistema embarcado), o melhor caso com OpenMP consumiu 2% menos energia que Pthreads; 6% menos que MPI-1; e 15% menos que MPI-2, para o mesmo conjunto de benchmarks. / In current computer systems, while it is necessary to exploit the availability of multiple cores, it is also mandatory to consume less energy. To accelerate the development of parallel applications and to make it more transparent to the programmer, Parallel APIs (Application Programming Interfaces) are widely used. However, each Parallel API implements different ways to exchange data using shared memory regions. These regions are generally more remote than the private ones, and therefore have greater access time and energy consumption. Furthermore, the memory system of embedded processors is different with regard to hierarchy, size, access time, energy consumption, etc., when compared to general purpose processors. Thus, considering the above scenario, with different Parallel APIs being used in multicore systems with different requirements, this work will show that each interface has different behavior in terms of performance, energy consumption and Energy-Delay Product (EDP), and that this behavior varies according to the characteristic of the application and the processor employed (general purpose or embedded). For example, as a result of this work, we have observed that Pthreads consumes 8% less energy than the best case of OpenMP; 12% less than MPI-1; and 8% less than MPI-2, considering all benchmarks on the Intel Core i7 (general purpose). In contrast, in the ARM Cortex-A9 processor (embedded system), the best case with OpenMP consumed 2% less energy than Pthreads; 6% less than MPI-1; and 15% less than MPI-2 for the same benchmarks set.

Nos sistemas computacionais atuais, enquanto é necessário explorar a disponibilidade de múltiplos núcleos, também é obrigatório consumir menos energia. Para acelerar o processo de desenvolvimento de aplicações paralelas e o tornar mais transparente ao programador, Interfaces de Programação Paralela (IPPs) são largamente utilizadas. Entretanto, cada IPP implementa diferentes formas para trocar dados usando regiões compartilhadas da memória. Estas regiões são, geralmente, mais distantes do processador do que regiões privadas da memória e, por consequência, possuem maior tempo de acesso e consumo de energia. Ademais, o sistema de memória dos processadores embarcados é diferente em hierarquia, tamanho, tempo de acesso, consumo de energia, etc., quando comparado aos processadores de propósito geral. Assim, considerando o cenário supracitado, com diferentes IPPs sendo utilizadas em sistemas multicore com diferentes requisitos, neste trabalho será mostrado que cada interface possui comportamento diferente em termos de desempenho, consumo de energia e Energy-Delay Product (EDP), e que este comportamento varia de acordo com a característica da aplicação e o processador utilizado (propósito geral ou embarcado). Por exemplo, Pthreads consome 8% menos energia que o melhor caso de OpenMP; 12% menos que MPI-1; e 8% menos que MPI-2, considerando todos os benchmarks no processador Intel Core i7 (propósito geral). Em contrapartida, no processador ARM Cortex-A9 (sistema embarcado), o melhor caso com OpenMP consumiu 2% menos energia que Pthreads; 6% menos que MPI-1; e 15% menos que MPI-2, para o mesmo conjunto de benchmarks. / In current computer systems, while it is necessary to exploit the availability of multiple cores, it is also mandatory to consume less energy. To accelerate the development of parallel applications and to make it more transparent to the programmer, Parallel APIs (Application Programming Interfaces) are widely used. However, each Parallel API implements different ways to exchange data using shared memory regions. These regions are generally more remote than the private ones, and therefore have greater access time and energy consumption. Furthermore, the memory system of embedded processors is different with regard to hierarchy, size, access time, energy consumption, etc., when compared to general purpose processors. Thus, considering the above scenario, with different Parallel APIs being used in multicore systems with different requirements, this work will show that each interface has different behavior in terms of performance, energy consumption and Energy-Delay Product (EDP), and that this behavior varies according to the characteristic of the application and the processor employed (general purpose or embedded). For example, as a result of this work, we have observed that Pthreads consumes 8% less energy than the best case of OpenMP; 12% less than MPI-1; and 8% less than MPI-2, considering all benchmarks on the Intel Core i7 (general purpose). In contrast, in the ARM Cortex-A9 processor (embedded system), the best case with OpenMP consumed 2% less energy than Pthreads; 6% less than MPI-1; and 15% less than MPI-2 for the same benchmarks set.

Nos sistemas computacionais atuais, enquanto é necessário explorar a disponibilidade de múltiplos núcleos, também é obrigatório consumir menos energia. Para acelerar o processo de desenvolvimento de aplicações paralelas e o tornar mais transparente ao programador, Interfaces de Programação Paralela (IPPs) são largamente utilizadas. Entretanto, cada IPP implementa diferentes formas para trocar dados usando regiões compartilhadas da memória. Estas regiões são, geralmente, mais distantes do processador do que regiões privadas da memória e, por consequência, possuem maior tempo de acesso e consumo de energia. Ademais, o sistema de memória dos processadores embarcados é diferente em hierarquia, tamanho, tempo de acesso, consumo de energia, etc., quando comparado aos processadores de propósito geral. Assim, considerando o cenário supracitado, com diferentes IPPs sendo utilizadas em sistemas multicore com diferentes requisitos, neste trabalho será mostrado que cada interface possui comportamento diferente em termos de desempenho, consumo de energia e Energy-Delay Product (EDP), e que este comportamento varia de acordo com a característica da aplicação e o processador utilizado (propósito geral ou embarcado). Por exemplo, Pthreads consome 8% menos energia que o melhor caso de OpenMP; 12% menos que MPI-1; e 8% menos que MPI-2, considerando todos os benchmarks no processador Intel Core i7 (propósito geral). Em contrapartida, no processador ARM Cortex-A9 (sistema embarcado), o melhor caso com OpenMP consumiu 2% menos energia que Pthreads; 6% menos que MPI-1; e 15% menos que MPI-2, para o mesmo conjunto de benchmarks. / In current computer systems, while it is necessary to exploit the availability of multiple cores, it is also mandatory to consume less energy. To accelerate the development of parallel applications and to make it more transparent to the programmer, Parallel APIs (Application Programming Interfaces) are widely used. However, each Parallel API implements different ways to exchange data using shared memory regions. These regions are generally more remote than the private ones, and therefore have greater access time and energy consumption. Furthermore, the memory system of embedded processors is different with regard to hierarchy, size, access time, energy consumption, etc., when compared to general purpose processors. Thus, considering the above scenario, with different Parallel APIs being used in multicore systems with different requirements, this work will show that each interface has different behavior in terms of performance, energy consumption and Energy-Delay Product (EDP), and that this behavior varies according to the characteristic of the application and the processor employed (general purpose or embedded). For example, as a result of this work, we have observed that Pthreads consumes 8% less energy than the best case of OpenMP; 12% less than MPI-1; and 8% less than MPI-2, considering all benchmarks on the Intel Core i7 (general purpose). In contrast, in the ARM Cortex-A9 processor (embedded system), the best case with OpenMP consumed 2% less energy than Pthreads; 6% less than MPI-1; and 15% less than MPI-2 for the same benchmarks set.

The performance gap between processor and memory continues to remain a major performance bottleneck in both application specific and general purpose processors. This thesis strives to ease the above bottleneck by exploiting the characteristics of the application domain to improve the cache organization for two distinct processor architectures: (1) application specific processors for packet forwarding, (2) general purpose processors. Packet forwarding algorithms make use of a trie data structure to determine the forwarding route. We observe that the locality characteristics of the nodes at various levels of such a trie are different. Nodes that are closer to the root node, especially those that are immediate children of the root node (level-one nodes), exhibit higher temporal locality than nodes lower down the trie. Based on this observation we propose a novel Heterogeneously Segmented Cache Architecture (HSCA) that uses separate caches for level-one and lower-level nodes, each with carefully chosen sizes. We also propose a new replacement policy to enhance the performance of HSCA. Performance evaluation indicates that HSCA results in up to 32% reduction in average memory access time over a unified cache that shares the same cache space among all levels of the trie. HSCA also outperforms a previously proposed results cache. The use of a large root branching factor in a forwarding trie forcefully introduces a large number of nodes at level-one. Among these, only nodes that cover prefixes from the routing table are useful while the rest, are superfluous. We find that as many as 75% of the level-one nodes are superfluous. This leads to a skewed distribution of useful nodes among the cache sets of the level-one nodes cache. We propose a novel two-level mapping framework that achieves a better nodes to cache set mapping and hence incurs fewer conflict misses. Two-level mapping first aggregates nodes into Initial Partitions (IPs) using lower order bits and then remaps them from IPs into Refined Partitions (RPs), that form sets, based on some higher order bits. It provides flexibility in placement by allowing each IP to choose a different remap function. We propose three schemes conforming to the framework. A speedup in average memory access time of as much as 16% is gained over HSCA. In general purpose processor architectures, the design objectives of caches at various levels of the hierarchy are different. To ensure low access latencies, L1 caches are small and have low associativities, making them more susceptible to conflict misses. The extent of conflict misses incurred is governed by the placement function and the memory access patterns exhibited by the program. We propose a mechanism to learn the access characteristics of the program at runtime by analyzing the repetitive phases of program. We then make use of the two-level mapping framework to dynamically adapt the placement function. Further, we elegantly incorporate two-level mapping into the cache organization without increasing the cache access latency. Performance evaluation reveals that the proposed adaptive placement mechanism eliminates 32—36% of misses on average over a range of cache sizes. To prevent expensive off-chip accesses, L2 caches are larger and have higher associativities. Hence, the replacement policy plays a significant role in determining L2 cache performance. Further, as the inherent temporal locality in memory accesses is filtered out by the L1 cache, an L2 cache using the widely prevalent LRU replacement policy incurs significantly higher misses than the optimal replacement policy (OPT). We propose to bridge this gap through a novel replacement strategy that mimics the replacement decisions of OPT. The L2 cache is logically divided into two components, a Shepherd Cache (SC) with a simple FIFO replacement and a Main Cache (MC) with an emulation of optimal replacement. The SC plays the dual role of caching lines and shepherding the replacement decisions close to optimal for MC. Our proposed organization can cover 40% of the gap between LRU and OPT, resulting in 7% overall speedup.

La problématique de cette thèse se place à l’interface entre le domaine scientifique du contrôle non destructif par ultrasons (CND US) et l’adéquation algorithme architecture. Le CND US comprend un ensemble de techniques utilisées pour examiner un matériau, qu’il soit en production ou maintenance. Afin de détecter d’éventuels défauts, de les positionner et les dimensionner, des méthodes d’imagerie et de reconstruction ont été développées au CEA-LIST, dans la plateforme logicielle CIVA.L’évolution du matériel d’acquisition entraine une augmentation des volumes de données et par conséquent nécessite toujours plus de puissance de calcul pour parvenir à des reconstructions en temps interactif. L’évolution multicoeurs des processeurs généralistes (GPP), ainsi que l’arrivée de nouvelles architectures comme les GPU rendent maintenant possible l’accélération de ces algorithmes.Le but de cette thèse est d’évaluer les possibilités d’accélération de deux algorithmes de reconstruction sur ces architectures. Ces deux algorithmes diffèrent dans leurs possibilités de parallélisation. Pour un premier, la parallélisation sur GPP est relativement immédiate, contrairement à celle sur GPU qui nécessite une utilisation intensive des instructions atomiques. Quant au second, le parallélisme est plus simple à exprimer, mais l’ordonnancement des nids de boucles sur GPP, ainsi que l’ordonnancement des threads et une bonne utilisation de la mémoire partagée des GPU sont nécessaires pour obtenir un fonctionnement efficace. Pour ce faire, OpenMP, CUDA et OpenCL ont été utilisés et comparés. L’intégration de ces prototypes dans la plateforme CIVA a mis en évidence un ensemble de problématiques liées à la maintenance et à la pérennisation de codes sur le long terme. / This thesis work is placed between the scientific domain of ultrasound non-destructive testing and algorithm-architecture adequation. Ultrasound non-destructive testing includes a group of analysis techniques used in science and industry to evaluate the properties of a material, component, or system without causing damage. In order to characterize possible defects, determining their position, size and shape, imaging and reconstruction tools have been developed at CEA-LIST, within the CIVA software platform.Evolution of acquisition sensors implies a continuous growth of datasets and consequently more and more computing power is needed to maintain interactive reconstructions. General purprose processors (GPP) evolving towards parallelism and emerging architectures such as GPU allow large acceleration possibilities than can be applied to these algorithms.The main goal of the thesis is to evaluate the acceleration than can be obtained for two reconstruction algorithms on these architectures. These two algorithms differ in their parallelization scheme. The first one can be properly parallelized on GPP whereas on GPU, an intensive use of atomic instructions is required. Within the second algorithm, parallelism is easier to express, but loop ordering on GPP, as well as thread scheduling and a good use of shared memory on GPU are necessary in order to obtain efficient results. Different API or libraries, such as OpenMP, CUDA and OpenCL are evaluated through chosen benchmarks. An integration of both algorithms in the CIVA software platform is proposed and different issues related to code maintenance and durability are discussed.

La simulation est de plus en plus utilisée dans le domaine industriel du Contrôle Non Destructif. Elle est employée tout au long du processus de contrôle, que ce soit pour en accélérer la mise au point ou en comprendre les résultats. Les travaux menés au cours de cette thèse présentent une méthode de calcul rapide de champ ultrasonore rayonné par un capteur multi-éléments dans une pièce isotrope, permettant un usage interactif des simulations. Afin de tirer parti des architectures parallèles communément disponibles, un modèle régulier (qui limite au maximum les branchements divergents) dérivé du modèle générique présent dans la plateforme logicielle CIVA a été mis au point. Une première implémentation de référence a permis de le valider par rapport aux résultats CIVA et d'analyser son comportement en termes de performances. Le code a ensuite été porté et optimisé sur trois classes d'architectures parallèles aujourd'hui disponibles dans les stations de calcul : le processeur généraliste central (GPP), le coprocesseur manycore (Intel MIC) et la carte graphique (nVidia GPU). Concernant le processeur généraliste et le coprocesseur manycore, l'algorithme a été réorganisé et le code implémenté afin de tirer parti des deux niveaux de parallélisme disponibles, le multithreading et les instructions vectorielles. Sur la carte graphique, les différentes étapes de simulation de champ ont été découpées en une série de noyaux CUDA. Enfin, des bibliothèques de calculs spécifiques à ces architectures, Intel MKL et nVidia cuFFT, ont été utilisées pour effectuer les opérations de Transformées de Fourier Rapides. Les performances et la bonne adéquation des codes produits ont été analysées en détail pour chaque architecture. Dans plusieurs cas, sur des configurations de contrôle réalistes, des performances autorisant l'interactivité ont été atteintes. Des perspectives pour traiter des configurations plus complexes sont dressées. Enfin la problématique de l'industrialisation de ce type de code dans la plateforme logicielle CIVA est étudiée. / The Non Destructive Testing field increasingly uses simulation.It is used at every step of the whole control process of an industrial part, from speeding up control development to helping experts understand results. During this thesis, a simulation tool dedicated to the fast computation of an ultrasonic field radiated by a phase array probe in an isotropic specimen has been developped. Its performance enables an interactive usage. To benefit from the commonly available parallel architectures, a regular model (aimed at removing divergent branching) derived from the generic CIVA model has been developped. First, a reference implementation was developped to validate this model against CIVA results, and to analyze its performance behaviour before optimization. The resulting code has been optimized for three kinds of parallel architectures commonly available in workstations: general purpose processors (GPP), manycore coprocessors (Intel MIC) and graphics processing units (nVidia GPU). On the GPP and the MIC, the algorithm was reorganized and implemented to benefit from both parallelism levels, multhreading and vector instructions. On the GPU, the multiple steps of field computing have been divided in multiple successive CUDA kernels.Moreover, libraries dedicated to each architecture were used to speedup Fast Fourier Transforms, Intel MKL on GPP and MIC and nVidia cuFFT on GPU. Performance and hardware adequation of the produced algorithms were thoroughly studied for each architecture. On multiple realistic control configurations, interactive performance was reached. Perspectives to adress more complex configurations were drawn. Finally, the integration and the industrialization of this code in the commercial NDT plateform CIVA is discussed.