The continued scaling of device dimensions in complementary metal oxide semiconductor (CMOS) technology within the sub-100 nm region requires an alternative high dielectric constant (high-k) oxide layer to counter high tunneling leakage currents, a metallic gate electrode to address polysilicon depletion, boron penetration and high polysilicon sheet resistance, and high mobility channel materials to boost the CMOS performance. Metal gates can also offer improved thermal and chemical stability, but their use requires that we improve our understanding of how the metal alloy phase, crystallographic orientation, and composition affect the electronic properties of the metal alloy-oxide interface. To replace n++ and p++ polysilicon gate electrodes and maintain scaled device performance requires metal gate electrodes with work functions within 0.2 eV of the silicon conduction and valence band edges, i.e., 5.0-5.2 and 4.1-4.3 eV, for PMOS and NMOS devices, respectively. In addition to work function and thermal/chemical stability, metal gates must be integrated into the CMOS process flow. It is the aim of this work to significantly expand our knowledge base in alloys for dual metal gates by carrying out detailed electrical and materials studies of the binary alloy systems of Ru with p-type metal Pt. Three n-type metals systems, Ru-Ta, Ru-Hf and Ru-Nb have also been partially investigated. This work also focuses on high mobility Ge p-MOSFETs for improved CMOS performance. DC magnetron sputtering has been used to deposit binary alloy films on thermally grown SiO2. The composition of the alloy films have been determined by Rutherford backscattering spectrometry and the identification of phases present have been made using x-ray and electron diffraction of samples. The microstructure of the phases of interest has been examined in the transmission electron microscope and film texture was characterized via x-ray diffraction. The electrical characterization includes basic resistivity measurements, and work function extraction. The work function has been determined from MOS capacitor and Schottky diodes. The need for electron and hole mobility enhancement and the progress in the development of high-k gate stacks, has lead to renewed interest in Ge MOSFETs. The p-MOS mobility data for Ge channel devices have been reported. The results indicate greater than 2 x improvements in device mobility as compared to standard Si device. A low frequency noise assessment of silicon passivated Ge p-MOSFETs with a TiN/TaN/HfO2 gate stack has been made. For the first time we also report results on low frequency noise characterisation for a Ge P+- n junctions with and without Ni germanidation.