Systems have been designed and synthesized using CMOS technology for many years, with improvements in the fabrication process allowing designs to be scaled onto smaller areas with relative ease. The introduction of nano scale CMOS technologies has ended this time of simple scaling, as variations within the silicon now dramatically affect circuit performance and manufacturing yield. These random physical variations cannot be removed from the manufacturing process, requiring that their affects are modelled, predicted and accommodated within the design process. This thesis presents an investigation into the challenges of including these affects within the design process, with a review of the recent research conducted in incorporating variability within timing analysis tools. The conclusion from the literature review is that an accurate, efficient and transparent method of predicting the impact of statistical process variations on the performance of a circuit has not yet been created and adopted by the IC design industry. The investigation begins with the modelling of transistor based statistical process variations at the standard cell level, where it is determined that simple statistical models do not accurately reflect the extremes in performance, and can provide overly pessimistic predictions. The techniques of Monte Carlo Cell Characterisation (MCCC) and Monte Carlo Static Timing Analysis (MCSTA) are introduced as more suitable approaches, which accurately reflect the performance of circuits as modelled by Monte Carlo SPICE simulations, with far less pessimism than the traditional method of Corner Analysis or even modern Statistical Static Timing Analysis. The final section of this thesis focuses on practical implementations of MCSTA, where the sample sizes required to accurately predict circuit behaviour (to within 1% of SPICE)can be reduced to as few as ten, using simple statistical sampling techniques.