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Multiple Instruction, Multiple Data (MIMD) networks can produce scalable processing power for a wide variety of image computing applications. For certain tasks however, data-distribution bottlenecks reduce the maximum achievable performance gain. Digital Signal Processing (DSP) technology is capable of high performance from a single processor, thus avoiding some of the data communication problems associated with multi-processor systems. Nevertheless, many practical applications require the incorporation of processing primitives provided by single computational elements, such as DSP, within a more general computational domain. The Fast Fourier Transform (FT) is typical of a class of algorithm frequently used in image processing that can be computed by a single DSP processor in the same time interval as a system containing many MIMD processors. The work investigates the design, construction and properties of a hierarchical computing system, capable of implementing complete FT transforms on two dimensional data structures. The basic hardware comprises a proprietary DSP processor, a controlling transputer and multiple, switched, banks of fast static random access memory (SRAM). The design strategy successfully allows the arithmetic operations of the DSP processor to be concurrent with the data exchange and input/output activities of the controlling transputer. The complexity of the resulting system prompted an investigation into structured design techniques. As the normal specification language Z has been shown to be a useful tool for software system design and documentation, its value in the design of a hardware system is explored. The way in which Z is utilised differs from existing applications to software system development, especially in the method of refinement towards a combined system of hardware, programmable logic and control software. After extensive design, construction and testing phases, initial validation shows that while the accelerator is a very powerful resource, capable of a complete 1024 point, one dimensional FFT in 560s, an efficiency of 45&'37 is difficult to exceed when repeated transforms are calculated.

El presente trabajo de investigación tiene por objetivo analizar las diferentes soluciones de virtualización del mercado informático y a partir de ello lanzar una propuesta el cuál priorice el principal beneficio de esta tecnología, el de reducir los costos de hardware. A continuación, un breve resumen de los incisos más importantes de los capítulos desarrollados. El capítulo 1: “Planteamiento del problema” describe 2 casos diferentes de dos instituciones educativas. El primer caso se presenta en el C.E.E. “Rafael Narváez Cadenillas” cuya preocupación es brindar una educación de calidad a su alumnado y parte ello es renovar los equipos de cómputo de su laboratorio. El segundo caso le pertenece a la I.E.E. “Antonio Raymondi” cuya deficiencia radica en no contar con la suficiente cantidad de equipos de cómputo para atender a su alumnado. El capítulo 2: “Marco teórico” inicia con los antecedentes de la virtualización, los tipos de virtualización que se desarrollaron con el transcurso del tiempo, tipos de hipervisores, definición de la virtualización de escritorio y arquitectura. Así mismo, se especifican los beneficios, ventajas y desventajas de implementarlo. El capítulo 3: “Metodología de la investigación” explica la metodología de la presente investigación haciendo referencia a algunos autores y sus definiciones. Estas definiciones ayudarán a entender y argumentar la selección del tipo y el diseño de la investigación, también se especifican la población y la muestra, las técnicas e instrumentos de recolección de datos; y finalmente se desarrolla la propuesta del plan de implementación. El capítulo 4: “Selección, análisis, elección y evaluación de soluciones software y hardware” obedece a la elección de las soluciones software y hardware que son utilizados en la propuesta de virtualización de escritorio. Posteriormente se plantea 4 modelos de virtualización para proceder con el análisis del costo total de propiedad y el retorno sobre la inversión. El capítulo 5 “Aplicación de la propuesta de virtualización para el C.E.E. Rafael Narváez Cadenillas y la I.E.E Antonio Raymondi” se desarrolla en base al plan de implementación propuesto donde en la etapa de análisis se calcula el ahorro que se genera tras implementar la virtualización de escritorio.

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Com o aumento crescente das capacidades dos circuitos integrado e conseqüente complexidade das aplicações, em especial as embarcadas, um requisito tem se tornado fundamental no desenvolvimento desses sistemas: ferramentas de desenvolvimento cada vez mais acessíveis aos engenheiros, permitindo, por exemplo, que um programa escrito em linguagem C possa ser convertido diretamente em hardware. Os FPGAs (Field Programmable Gate Array), elemento fundamental na caracterização de computação reconfigurável, é um exemplo desse crescimento, tanto em capacidade do CI como disponibilidade de ferramentas. Esse projeto teve como objetivos: estudar algumas ferramentas de conversão C, C++ ou Java para hardware reconfigurável; estudar benchmarks a serem executadas nessas ferramentas para obter desempenho das mesmas, e ter o domínio dos conceitos na conversão de linguagens de alto nível para hardware reconfigurável. A plataforma utilizada no projeto foi a da empresa Xilinx XUP V2P / With the growing capacities of Integrated Circuits (IC) and the complexity of the applications, especially in embedded systems, there are now requisites for developing tools that convert algorithms C direct into the hardware. As a fundamental element to characterize Reconfigurable Computing, FPGA (Field Programmable Gate Array) is an example of those CIs, as well as the tools that have been developed. In this project we present different tools to convert C into the hardware. We also present benchmarks to be executed on those tools for performance analysis. Finally we conclude the project presenting results relating the experience to implement C direct into the hardware. The Xilinx XUP V2P platform was used in the project

Made available in DSpace on 2019-03-30T00:14:13Z (GMT). No. of bitstreams: 0 Previous issue date: 2018-06-25 / Com a crescente demanda pela utilização de sistemas embarcados que estão substituindo complexos circuitos eletrônicos, surgiu a iniciativa da criação de uma metodologia computacional capaz de realizar o monitoramento com a utilização do microcontrolador Arduino com seus sensores disponibilizados e pré-configurados. O sistema desenvolvido denominado de Ardnom surgiu com o objetivo de estabelecer a comunicação com os Arduinos para poder através de plugins desenvolvidos como escopo da solução, realizar tarefas pré-configuradas definidas pelo usuário. A utilização do Ardnom através de experimentos apresentados no trabalho, verificou-se que o sistema se molda a diferentes tipos de cenários para idealizar um mesmo fim, que é o monitoramento utilizando Arduinos através de sensores para coletas e atuações sobre determinadasinformações. Palavras-chave: Monitoramento. Arduino. Sistemas Embarcados. Sensores

Made available in DSpace on 2019-03-29T23:23:10Z (GMT). No. of bitstreams: 0 Previous issue date: 2010-09-17 / When we talk about quality of software we think soon in various models and methodologies that are applied in the development process, whether in academia or in business, but when we talk about developing software and hardware together, so the question is how do we integrate these two coupling product ensuring and maintaining quality? To answer these questions we present the experience of defining a software development process to be used by companies that develop computer systems that are or want to implement the first level of MPS.BR. Keywords: embedded software, Process of developing computer systems / Quando falamos de qualidade de software pensamos logo em vários modelos e metodologias que são aplicadas no processo de desenvolvimento, seja na academia ou nas empresas. Porém, quando falamos em desenvolver software e hardware juntos, vem logo a pergunta: como vamos integrar estas duas realidades garantindo a qualidade? Para tentar ajudar a solucionar este problema, apresentamos neste trabalho a experiência de definição de um processo de desenvolvimento de software para ser utilizado por empresas que desenvolvem sistemas computacionais e que estejam ou queiram implementar o primeiro nível do MPS.BR. Palavras-chave: Software embarcado, Processo de desenvolvimento sistemas computacionais

The CADR machine, a revised version of the CONS machine, is a general-purpose, 32-bit microprogrammable processor which is the basis of the Lisp-machine system, a new computer system being developed by the Laboratory as a high-performance, economical implementation of Lisp. This paper describes the CADR processor and some of the associated hardware and low-level software.

The Supercomputer Toolkit is a proposed family of standard hardware and software components from which special-purpose machines can be easily configured. Using the Toolkit, a scientist or an engineer, starting with a suitable computational problem, will be able to readily configure a special purpose multiprocessor that attains supercomputer-class performance on that problem, at a fraction of the cost of a general purpose supercomputer. The Toolkit is currently being built as a joint project between Hewlett-Packard and MIT. The software and the applications are in various stages of development and research.

Reinforcement Learning (RL) is a machine learning discipline in which an agent learns by interacting with its environment. In this paradigm, the agent is required to perceive its state and take actions accordingly. Upon taking each action, a numerical reward is provided by the environment. The goal of the agent is thus to maximize the aggregate rewards it receives over time. Over the past two decades, a large variety of algorithms have been proposed to select actions in order to explore the environment and gradually construct an e¤ective strategy that maximizes the rewards. These RL techniques have been successfully applied to numerous real-world, complex applications including board games and motor control tasks. Almost all RL algorithms involve the estimation of a value function, which indicates how good it is for the agent to be in a given state, in terms of the total expected reward in the long run. Alternatively, the value function may re‡ect on the impact of taking a particular action at a given state. The most fundamental approach for constructing such a value function consists of updating a table that contains a value for each state (or each state-action pair). However, this approach is impractical for large scale problems, in which the state and/or action spaces are large. In order to deal with such problems, it is necessary to exploit the generalization capabilities of non-linear function approximators, such as arti…cial neural networks. This dissertation focuses on practical methodologies for solving reinforcement learning problems with large state and/or action spaces. In particular, the work addresses scenarios in which an agent does not have full knowledge of its state, but rather receives partial information about its environment via sensory-based observations. In order to address such intricate problems, novel solutions for both tabular and function-approximation based RL frameworks are proposed. A resource-efficient recurrent neural network algorithm is presented, which exploits adaptive step-size techniques to improve learning characteristics. Moreover, a consolidated actor-critic network is introduced, which omits the modeling redundancy found in typical actor-critic systems. Pivotal concerns are the scalability and speed of the learning algorithms, for which we devise architectures that map efficiently to hardware. As a result, a high degree of parallelism can be achieved. Simulation results that correspond to relevant testbench problems clearly demonstrate the solid performance attributes of the proposed solutions.