We propose in this paper an algebraic approach to hard-ware/software partitioning in Verilog Hardware Description Language (HDL). We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog. Through this, we confirm successful verification for the correctness of the partitioning process by an algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems. / Singapore-MIT Alliance (SMA)

Application profiling is an important step in the design and optimization of embedded systems. Accurately identifying and analyzing the execution of frequently executed computational kernels is needed to effectively optimize the system implementation, both at design time and runtime. In a traditional design process, it suffices to perform the profiling and optimization steps offline, during design time. The offline profiling guides the design space exploration, hardware software codesign, or power and performance optimizations. When the system implementation can be finalized at design time, this approach works well. However, dynamic optimization techniques, which adapt and reconfigure the system at runtime, require dynamic profiling with minimum runtime overheads. Existing profiling methods are usually software based and incur significant overheads that may be prohibitive or impractical for profiling embedded systems at runtime. In addition, these profiling methods typically focus on profiling the execution of specific tasks executing on a single processor core, but do not consider accurate and holistic profiling across multiple processor cores. Directly utilizing existing profiling approaches and naively combining isolated profiles from multiple processor cores can lead to significant profile inaccuracies of up to 35%. To address these challenges, a hardware-based dynamic application profiler for non-intrusively and accurately profiling software applications in multicore embedded systems is presented. The profiler provides a detailed execution profile for computational kernels and maintains profile accuracy across multiple processor cores. The hardware-based profiler achieves an average error of less than 0.5% for the percentage execution time of profiled applications while being area efficient.

Field Programmable Gate Arrays (FPGAs) are a reconfigurable hardware platform which enable the acceleration of software code through the use of custom-hardware circuits. Complex systems combining processors with programmable logic require partitioning to decide which code segments to accelerate. This thesis provides tools to help determine which software code sections would most benefit from hardware acceleration. A low-overhead profiling architecture, called LEAP, is proposed to attain real-time profiles of an FPGA-based processor. LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated and implemented to identify candidate software for acceleration. 1) Cycle profiling determines the most time-consuming functions to maximize speedup. 2) Cache stall profiling detects memory-intensive code; large memory overheads reduce the benefits of acceleration. 3) Energy consumption profiling detects energy-inefficient code through the use of an instruction-level power database to minimize the system's energy consumption.

Field Programmable Gate Arrays (FPGAs) are a reconfigurable hardware platform which enable the acceleration of software code through the use of custom-hardware circuits. Complex systems combining processors with programmable logic require partitioning to decide which code segments to accelerate. This thesis provides tools to help determine which software code sections would most benefit from hardware acceleration. A low-overhead profiling architecture, called LEAP, is proposed to attain real-time profiles of an FPGA-based processor. LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated and implemented to identify candidate software for acceleration. 1) Cycle profiling determines the most time-consuming functions to maximize speedup. 2) Cache stall profiling detects memory-intensive code; large memory overheads reduce the benefits of acceleration. 3) Energy consumption profiling detects energy-inefficient code through the use of an instruction-level power database to minimize the system's energy consumption.

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Dans cette thèse, nous avons adapté trois versions d'une chaine d'algorithmes de reconnaissance biométrique par l’iris appelés OSIRIS V2, V3, V4 qui correspondent à différentes implémentations de l’approche de J. Daugman pour les besoins d’une implémentation logicielle / matérielle. Les résultats expérimentaux sur la base de données ICE2005 montrent que OSIRIS_V4 est le système le plus fiable alors qu’OSIRIS_V2 est le plus rapide. Nous avons proposé une mesure de qualité de l’image segmentée pour optimiser en terme de compromis coût / performance un système de référence basé sur OSIRIS V2 et V4. Nous nous sommes ensuite intéressés à l’implémentation de ces algorithmes sur des plateformes reconfigurables. Les résultats expérimentaux montrent que l’implémentation matériel / logiciel est plus rapide que l’implémentation purement logicielle. Nous proposons aussi une nouvelle méthode pour le partitionnement matériel / logiciel de l’application. Nous avons utilisé la programmation linéaire pour trouver la partition optimale pour les différentes tâches prenant en compte les trois contraintes : la surface occupée, le temps d’exécution et la consommation d’énergie / In this thesis, we adapted three versions of a chain of algorithms for biometric iris recognition called OSIRIS V2, V3, V4, which correspond to different implementations of J. Daugman approach. The experimental results on the database ICE2005 show that OSIRIS_V4 is the most reliable when OSIRIS_V2 is the fastest. We proposed a measure of quality of the segmented image in order to optimize in terms of cost / performance compromise a reference system based on OSIRIS V2 and V4. We focused on the implementation of these algorithms on reconfigurable platforms. The experimental results show that the hardware / software implementation is faster than the software implementation. We propose a new method for partitioning hardware / software application. We used linear programming to find the optimal partition for different tasks taking into account the three constraints : the occupied area, execution time and energy consumption

En raison de ses avantages inhérents, tels que son faible coût, sa fiabilité élevée, sa capacité de fonctionnement à grande vitesse et en environnements difficiles, la machine à réluctance variable (MRV) est une solution attrayante pour l'industrie automobile. Cependant, la traction automobile est une application pour laquelle le comportement acoustique du groupe motopropulseur doit être particulièrement considéré, dans l'optique de ne pas dégrader le confort des passagers. Afin de rendre la MRV compétitive pour cette application automobile, le travail présenté se concentre sur plusieurs méthodes de contrôle cherchant à améliorer le comportement acoustique des MRV en réduisant les vibrations d'origine électromagnétique. Un modèle multi-physique électromagnétique / mécanique semi-analytique est proposé à partir de résultats de simulation numérique obtenus par la méthode des éléments finis. Ce modèle multiphysique est composé de modèles électromagnétiques et structurels, qui sont reliés par la composante radiale de la force électromagnétique. Deux méthodes de contrôle sont ensuite proposées. La première réduit la vibration en faisant varier l'angle de coupure du courant, la fréquence du la variation étant basée sur les propriétés mécaniques de la structure MRV. De plus, une fonction aléatoire uniformément distribuée est introduite pour éviter une composante fréquentielle locale de forte vibration. Une seconde méthode est basée sur le contrôle direct de la force (DFC), qui vise à obtenir une force radiale globale plus douce pour réduire les vibrations. Un adaptateur de courant de référence (RCA) est proposé pour limiter l'ondulation de couple introduite par le DFC, provoquée par l'absence de limitation de courant. Cette seconde méthode de réduction des vibrations appelée DFC & RCA est évaluée par des tests expérimentaux utilisant un prototype de MRV 8/6 afin de montrer sa pertinence. Une solution de partitionnement hardware/software est proposée pour implémenter cette méthode sur une carte FPGA utilisée en combinaison avec un microprocesseur. / Due to its inherent advantages Switched Reluctance Machine (SRM) are appealing to the automotive industry. However, automotive traction is a very noise sensitive application where the acoustic behavior of the power train may be the distinction between market success and market failure. To make SRM more competitive in the automotive application, this work will focus on the control strategy to improve the acoustic behavior of SRM by vibration reduction. A semi-analytical electromagnetic/structural multi-physics model is proposed based on the simulation results of numerical computation. This multi-physics model is composed by electromagnetic and structural models, which are connected by the radial force. Two control strategies are proposed. The first strategy to improve the acoustic behavior of SRM by vibration reduction. A semi-analytical electromagnetic/ structural multi-physics model is proposed based on the simulation results of numerical computation. This multi-physics model is composed by electromagnetic and structural models, which are connected by the radial force. Two control strategies are proposed. The first one reduces the vibration by varying the turn-off angle, the frequency of the variable signal is based on the mechanical property of switched reluctance machine. Besides, an uniformly distributed random function is introduced to avoid local high vibration component. Another one is based on the Direct Force Control (DFC), which aims to obtain a smoother total radial force to reduce the vibration. An reference current adapter (RCA) is proposed to limit the torque ripple introduced by the DFC, which is caused by the absence of the current limitation. The second vibration reduction strategy named DFC&RCA is evaluated by experimental tests using an 8/6 SRM prototype. A hardware/software partitioning solution is proposed to implement this method, where FPGA board is used combined with a Microprocessor.