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It is often required in communication and navigation systems to be able to receive signals from multiple stations simultaneously. A common practice to do this is to use multiple hardware resources; a different set of resources for each station. In this thesis, a Coherent Amplitude Modulated (AM) receiver system was developed based on Software Defined Radio (SDR) technology enabling reception of multiple signals using hardware resources needed only for one station. The receiver system architecture employs Time Division Multiplexing (TDM) to share the single hardware resource among multiple streams of data. The architecture is designed so that it can be minimally modified to support any number of stations. The Verilog Hardware Description Language (HDL) was used to capture the receiver system architecture and design. The design and architecture are initially validated using HDL post-synthesis and post-implementation simulation. In addition, the receiver system architecture and design were implemented to a Xilinx Field Programmable Gate Array (FPGA) technology prototyping board for experimental testing and final validation.

Orientador: Luís Geraldo Pedroso Meloni / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-23T18:38:54Z (GMT). No. of bitstreams: 1 BarraganGuerrero_DiegoOrlando_M.pdf: 4412718 bytes, checksum: fd7daf7712cace2d176bf47e3bd792dd (MD5) Previous issue date: 2013 / Resumo: Os sistemas OFDM são intrinsecamente sensíveis a erros de sincronismo de tempo e frequência. O sincronismo é uma etapa fundamental para a correta recepção de pacotes. Esta dissertação descreve como se implementar vários algoritmos de sincronismo para OFDM em FPGA usando os símbolos do preâmbulo definidos no padrão IEEE 802.11a. Além disso, foi implementado o algoritmo CORDIC (necessário para a etapa de estimação e compensação de desvio de portadora) em modo rotacional e vetorial para um sistema coordenado circular, comparando o desempenho de várias arquiteturas com o intuito de otimizar a frequência de operação e relacionar o erro do resultado com o número de iterações realizadas. Conforme mostrado nos resultados, são obtidas estimativas com boas aproximações para desvios de 0, 100 e 200 kHz. Os resultados obtidos constituem um instrumento importante para a melhor escolha de implementação de algoritmos de sincronismo em FPGA. Verificou-se que os diferentes algoritmos não apenas possuem valores de variância distintos, mas também frequências de operação diferentes e consumo de recursos da FPGA. Ao longo do projeto foi considerado um modelo de canal tapped-delay / Abstract: OFDM systems are intrinsically sensitive to errors of synchronization in time and frequency. Synchronization is a key step for correct packet reception. This thesis describes how to implement in FPGA several synchronization algorithms for OFDM using the symbols of the preamble defined in IEEE 802.11a. In addition, the CORDIC algorithm is implemented (step required for carrier frequency offset estimation and compensation) in rotational and vectoring mode for a circular coordinate system, comparing the performance of various architectures in order to optimize the operating frequency and relate the error of the result with the number of iterations performed. As shown in the results, estimates are obtained with good approximations for offsets of 0, 100 and 200 kHz. The obtained results are an important instrument for the best choice of synchronization algorithm for implementation in FPGA. It was found that the different algorithms have not only different values of variance, but also different operating frequency and consumption of the FPGA resources. Throughout the project a tapped-delay channel model was considered in the analysis / Mestrado / Telecomunicações e Telemática / Mestre em Engenharia Elétrica