As modern embedded systems are becoming more sophisticated the demands on their applications significantly increase. A current trend is to utilize the advances of heterogeneous platforms (i.e. platform consisting of different computational units (e.g. CPU, FPGA or GPU)) where different parts of the application can be distributed among the different computational units as software and hardware implementations. This technology can improve the application characteristics to meet requirements (e.g. execution time, power consumption and design cost), but it leads to a new challenge in finding the best combination of hardware and software implementation (referred as system configuration). The decisions whether a part of the application should be implemented in software (e.g. as C code) or hardware (e.g. as VHDL code) affect the entire product life-cycle. This is traditionally done manually by the developers in the early stage of the design phase. However, due to the increasing complexity of the application the need of a systematic process that aids the developer when making these decisions to meet the demands rises. Prior to this work a methodology called MULTIPAR has been designed to address this problem. MULTIPAR applies component-/model-based techniques to design the application, i.e. the application is modeled as a number of interconnected components, where some of the components will be implemented as software and the remaining ones as hardware. To perform the partitioning decisions, i.e. determining for each component whether it should be implemented as software or hardware, MULTIPAR proposes a set of formulas to calculate the properties of the entire system based on the properties for each component working in isolation. This thesis aims to show to what extent the proposed system formulas are valid. In particular it focuses on validating the formulas that calculate the system response time, system power consumption, system static memory and system FPGA area. The formulas were validated trough an industrial case study, where the system properties for different system configurations were measured and calculated by applying these formulas. The measured values and calculated values for the system properties were compared by conducting a statistical analysis. The case study demonstrated that the system properties can be accurately calculated by applying the system formulas.

Heterogeneous platforms, systems with both general-purpose processors and task-specific hardware, are largely used in industry to increase efficiency, but the heterogeneity also increases the difficulty of design and verification. We often need to wait for the completion of all the modules to know whether the functionality of the design is correct or not, which can cause costly and tedious design iteration cycles. Correctness by construction is a methodology that proposes tackling this problem by separating specification and implementation and bridging them through formal methods. Code synthesis is one of these methods which refers to the process of generating low-level codes implementing the desired system from high-level modelling languages. Formulating a generic synthesis method can, in principle, decrease error rates and shorten development cycles since target-specific usage and mechanisms can be systematically taken care of in an automatic manner, whereas the designer needs only to ensure the functional correctness of the high-level specification model. In this respect, this thesis aims to use the open-source Zero Overhead Topology Infrastructure (ZOTI) methodology to formulate a synthesis process from a denotational graph-based representation of an application, tailored towards heterogeneous hardware/software implementations. The case study presents the partially automated synthesis of an open-source streaming processing subsystem on a Xilinx Zynq-based system-on-chip architecture consisting of a software part and a custom hardware accelerator part, where both C software and VHDL hardware are generated from the input model. While the initial results demonstrate a promising path for systemizing the code generation process, certain aspects of the synthesis, such as generating glue code for complex data types (e.g., multi-arrays), are left out of the scope of this thesis and will be explored in future work. / Heterogena plattformar, system med både generella processorer och uppgiftsspecifik hårdvara, används till stor del inom industrin för att öka effektiviteten, men heterogeniteten ökar också svårigheten att designa och verifiera. Vi behöver ofta vänta på att alla moduler är färdiga för att veta om designens funktionalitet är korrekt eller inte, vilket kan orsaka kostsamma och tråkiga designiterationscykler. Korrekthet genom konstruktion är en metod som föreslår att man åtgärdar detta problem genom att separera specifikation och implementering och överbrygga dem genom formella metoder. Kodsyntes är en av dessa metoder som hänvisar till processen att generera lågnivåkoder som implementerar det önskade systemet från högnivåmodelleringsspråk. Att formulera en generisk syntesmetod kan i princip minska felfrekvensen och förkorta utvecklingscyklerna eftersom målspecifik användning och mekanismer systematiskt kan tas om hand på ett automatiskt sätt, medan designern bara behöver säkerställa den funktionella korrektheten hos högnivån. specifikationsmodell. I detta avseende syftar denna avhandling till att använda öppen källkod Zero Overhead Topology Infrastructure (ZOTI) metodiken för att formulera en syntesprocess från en denotationsgrafbaserad representation av en applikation, skräddarsydd för heterogena hårdvaru-/mjukvaruimplementationer. Fallstudien presenterar den delvis automatiserade syntesen av ett undersystem för bearbetning av strömning med öppen källkod på en Xilinx Zynq-baserad system-på-chip-arkitektur bestående av en mjukvarudel och en anpassad hårdvaruacceleratordel, där både C-programvara och VHDL-hårdvara genereras från ingångsmodellen. Även om de initiala resultaten visar en lovande väg för att systemisera kodgenereringsprocessen, lämnas vissa aspekter av syntesen, såsom generering av limkod för komplexa datatyper (t.ex. multi-arrayer), utanför ramen för denna avhandling och kommer att vara utforskas i framtida arbete.