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The scaling down of Complementary Metal Oxide Semiconductor (CMOS) transistors to sub-100nm requires replacement of conventional Silicon dioxide layer with high dielectric constant (K) material for gate dielectric. Among the various high-K dielectrics that have been studied, HfO2 is found to be a promising candidate because of its high dielectric constant (~25), large band gap (5.68 eV), thermodynamic stability and good interface with Si. The HfO2 films have already been deposited using different growth techniques such as Atomic layer Deposition (ALD), Metalorgonic Chemical Vapor Deposition (MOCVD) and Pulsed Laser Deposition (PLD). Ion Assisted Deposition (IAD) is a novel technique that has been successfully employed to produce optical coatings of required quality. This growth technique presents many advantages over the other techniques such as formation from solid oxide sources, low growth temperatures (25-3000C) and film densification by ion bombardment. Hence this technique has been used to prepare HfO2 films in the present investigations. This thesis presents the structural, optical and electrical properties of HfO2 thin films prepared by Ion assisted deposition (IAD). The suitability of Ion assisted deposition process and the importance of investigations on the influence of process parameters on the film characteristics have been brought out in the process parameters-structure-composition and properties correlation presented in this thesis. The aim of this work is to process and characterize HfO2 films and investigate the influence of process parameters on the structure, composition and properties of the films to identify their suitability for CMOS gate applications. HfO2 films were deposited on p-type Si (100) wafers by Ion assisted deposition in an electron beam evaporation (Leybold,L-560) system. Pre-bombardment of the substrates with Argon ions has been done to remove any native oxide layer formation on Silicon by using a hallow cathode ion source (DENTON VACUUM CC103). During the film deposition a collimated oxygen ion beam, generated from the ion source is directed towards the substrate. The oxygen ion current is controlled by adjusting the voltage applied to the ion source and the oxygen flow through the ion source. The oxygen ions bombard the film as it grows and in that process improves its packing density as well as its stoichiometry. Keeping the deposition rate and thickness constant, HfO2 films have been deposited by varying Ion Current, Ion energy and substrate temperature. MOS capacitors were fabricated with Aluminum as gate electrode deposited by thermal evaporation. Ellipsometry techniques have been used to measure the optical thickness of the films. The interfacial layer (IL) formed at the HfO2/ Si interface was investigated by using Fourier transform Infrared spectroscopy (FT-IR). The structural characterization was carried out by X-ray diffraction technique. The high frequency capacitance-voltage and DC leakage current characteristics were measured to analyze the electrical characteristics of MOS capacitors. The effect of post deposition annealing (PDA) of the films at 600°C and 700ºC in Forming Gas (15%H2+85%N2) ambient and Post metallization annealing (PMA) at 400ºC in the same ambient was also investigated to observe the changes in electrical characteristics. The initial step of this work was to compare the characteristics of the films deposited by reactive evaporation and Ion assisted deposition which confirmed the superiority of the quality of IAD coatings and justified the need to proceed further with a more detailed study on the influence of various parameters on the properties of IAD coatings. HfO2 films deposited on substrates maintained at 1000C exhibited better structural, Optical and Electrical properties. The leakage current in these films were lower which has been attributed to silicate free interface as confirmed by XRD studies. Investigations on films deposited with oxygen ion beams of different currents in the range 20 to 40mA indicated that the films deposited at 20mA ion current showed better electrical properties. Better stoichiometry of these films as indicated by FT IR studies was one of the reasons for their improved performance. Annealing of these films at 6000C and 7000C in FGA medium resulted in creation of silicates and silicides at the interface thereby increasing the leakage currents and degraded the film properties. The films deposited with oxygen ion beams generated with a driving voltage 265V showed better structural and optical properties with silicate free interface compared with low and high driving voltages. Among all the films, the maximum dielectric constant of about 21.9 with a minimum EOT of 5.5 nm corresponding to a film deposited at ion current 20mA with PMA 400°C in FG ambient for 20minites is achieved. The lowest value of interface charge density achieved is 2.7 x1012 per cm-2 eV-1 corresponding to the sample deposited at substrate temperature 100°C with deposition rate of 0.5Å/sec followed by post metallization annealing at 400°C in forming gas for 20minutes. The range of Dit values that were obtained are varying from 2.7x 1012 – 16.7x1012 cm-2eV-1.It was also found that, the samples deposited at higher ion currents show lower Dit values than the samples deposited at lower ion currents. From the I−V analysis, the leakage current density is found to be comparatively less in IAD than in reactive evaporation. Leakage current increases with increase in substrate temperature and the same trend is observed with annealed films also. The lowest leakage current density of 1.05x10–8 A/cm2 at a gate bias of 1V was observed in the films deposited at substrate temperature 1000C. The present thesis focused on the suitability of the Ion Assisted deposition process for the preparation of HfO2 films for high-K gate dielectric application and the importance of investigations on the influence of process parameters on the film characteristics.

The continuous downscaling has enforced the device size and oxide thickness to few nanometers. After serving for several decades as an excellent gate oxide layer in complementary metal oxide semiconductor (CMOS) devices, the thickness of SiO2 layer has reached to its theoretical limits. Ultra-thin films of SiO2 can result in severe leakage currents due to direct tunneling as well as maintaining the homogeneity of the layers becomes an additional challenge. The use of a high- (HK) layer can solve these twin concerns of the semiconductor industry, which can also enhance the capacitance due to superior dielectric permittivity and reduce the leakage current by being thicker than the silicon dioxide. This thesis is concerned about the development of solution route fabricated high-k (TiO2, ZrO2 and HfO2) gate dielectrics and the investigation of high-/silicon interfaces by highly sensitive DLTS technique in MOS structures. The solution processing reduce the industrial fabrication cost and the DLTS method has the advantage to accurately measure the interface related defects parameters; such as interface trap density (Dit), capture cross-section (), activation energy (ET) and also distinguish between bulk and interface traps. In this thesis, HK films have been deposited by solution route, the material and electrical properties of the film and the HK/Si interface have been extensively evaluated. IN CHAPTER 1, we have summarized the history and evolution of transistor and it provides the background for the work presented in this thesis. IN CHAPTER 2, we have described the experimental method /technique used for the fabrication and characterization. The advantages and working principals of spin-coating and DLTS techniques are summarized. IN CHAPTER 3, we have presented the preparation and optimization of TiO2 based HK layer. Structural, surface morphology, optical electrical and dielectric properties are discussed in details. A high- 34 value is achieved for the 36 nm TiO2 films. IN CHAPTER 4, we presented the technologically relevant Si/TiO2 interface study by DLTS technique. The DLTS analysis reveals a small capture cross-section of the interface with acceptable interface state density. IN CHAPTER 5, we have focused on the fabrication of amorphous ZrO2 films on p-Si substrate. The advantage of amorphous dielectric layer is summarized as first dielectric reported SiO2 is used in its amorphous phase. The moderate-15 with low leakage current density is achieved. IN CHAPTER 6, the HfO2 films are prepared using hafnium isopropoxide and a high value of dielectric constant 23 is optimized with low leakage current density. The current conduction mechanisms are discussed in details. IN CHAPTER 7, we have probed the oxygen vacancy related sub-band-gap states in HfO2 by DLTS technique. IN CHAPTER 8, we have presented the summary of the dissertation and the prospect research directions are suggested. In summary, we have studied the group IVB transition metal elemental oxides (TMEO); TiO2, ZrO2 and HfO2 thin films in the MOS structure, as a possible replacement of SiO2 gate dielectric. For the TMEO films deposition a low-cost and simple method spin-coating was utilized. The film thicknesses are in the range of 35 – 39 nm, which was measured by ellipsometry and confirmed with the cross-sectional SEM. A rough surface of gate dielectric layer can trap the charge carrier and may cause the Fermi level pinning, which can cause the threshold voltage instabilities. Hence, surface roughness of oxide layer play an important role in CMOS device operation. We have achieved quite good flat surfaces (RMS surface roughness’s are 0.2 – 2.43 nm) for the films deposited in this work. The TiO2 based MOS gate stack shows an optimized high dielectric constant ( 34) with low leakage current density (3.710-7 A.cm-2 at 1 V). A moderate dielectric constant ( 15) with low leakage current density (4.710-9 A.cm-2 at 1 V) has been observed for the amorphous ZrO2 thin films. While, HfO2 based MOS gate stack shows reasonably high dielectric constant ( 23) with low leakage current density (1.410-8 A.cm-2 at 1 V). We have investigated the dominating current conduction mechanism and found that the current is mainly governed by space charge limited conduction (SCLC) mechanism for the high bias voltages, while low and intermediate bias voltages show the (Poole – Frenkel) PF and (Fowler – Nordheim) FN tunneling, respectively. For the HfO2 MOS device band alignment is drawn from the UPS and J-V measurements. The band gap and electron affinity of HfO2 films are estimated 5.9 eV and 3 eV, respectively, which gives a reasonable conduction band offset (1.05 eV) with respect to Si. A TMEO film suffers from a large number of intrinsic defects, which are mostly oxygen vacancies. These defects can create deep levels below the conduction band of high- dielectric material, which can act like a hole and electron traps. In addition to that, interface between Si and high- is an additional concern. These defect states in the band gap of high- or at the Si/ high- interface might lead to the threshold voltage shifts, lower carrier mobility in transistor channel, Fermi level pinning and various other reliability issues. Hence, we also studied bulk and interfacial defects present in the high- films on Si and their interface with Si by a very sensitive DLTS technique. The capture cross-sections are measured by insufficient filling DLTS (IF – DLTS). The defects present at the interface are Si dandling bond and defect in the bulk are mostly oxygen vacancies related defects present in various charge states. The interface states (Dit) are in the range of 2×1011 to 9×1011 eV-1cm-2, which are higher than the Al/SiO2/Si MOS devices (Dit in Al/SiO2/Si is the benchmark and in the order of 1010 eV-1cm-2). Still this is an acceptable value for Si/high-k (non-native oxide) MOS devices and consistent with other deposition methods. The capture cross-sections are found to be quite low in the order of 10-18 to 10-19 cm2, which indicate a minor impact on the device operation. The small value of capture cross-sections are attributed to the involvement of tunneling, to and from the bulk traps to the interface. In conclusion, the low cost solution processed high- thin films obtained are of high quality and find their importance as a potential dielectric layer. DLTS study will be helpful to reveal various interesting facts observed in high- such as resistive switching, magnetism and leakage current problems mediated by oxygen vacancy related defects

Recently, high-κ materials have become the focus of research and been extensively utilized as the gate dielectric layer in aggressive scaled complementary metal-oxide-semiconductor (CMOS) technology. Hafnium dioxide (HfO2) is the most promising high-κ material because of its excellent chemical, thermal, mechanical and dielectric properties and also possesses good thermodynamic stability and better band offsets with silicon. Hence, HfO2 has already been used as gate dielectric in modern CMOS devices. For future technologies, it is very difficult to scale the silicon transistor gate length, so it is a necessary requirement of replacing the channel material from silicon to some high mobility material. Two-dimensional layered materials such as graphene and molybdenum disulfide (MoS2) are potential candidates to replace silicon. Due to its planar structure and atomically thin nature, they suit well with the conventional MOSFET technology and are very stable mechanically as well as chemically. HfO2 plays a vital role as a gate dielectric, not only in silicon CMOS technology but also in future nano-electronic devices such as graphene/MoS2 based devices, since high-κ media is expected to screen the charged impurities located in the vicinity of channel material, which results in enhancement of carrier mobility. So, for sustenance and enhancement of new technology, extensive study of the functional materials and its processing is required. In the present work, optimization of HfO2 thin films for gate dielectric applications in Nano-electronic devices using electron beam evaporation is discussed. HfO2 thin films have been optimized in two different thickness regimes, (i) about 35 nm physical thicknesses for back gate oxide graphene/MoS2 transistors and (ii) about 5 nm physical thickness to get Equivalent Oxide Thickness (EOT) less than 1 nm for top gate applications. Optical, chemical, compositional, structural and electrical characterizations of these films have been done using Ellipsometry, X-ray Photoelectron Spectroscopy (XPS), Rutherford Back Scattering (RBS), X-ray Diffraction (XRD), Capacitance-Voltage and Current-Voltage characterization techniques. The amount of O2 flow rate, during evaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post deposition annealing (PDA) and post metallization annealing (PMA) in forming gas ambient (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O2 flow rate shows the best properties as measured on MOS capacitors. A high density film (ρ=8.2 gram/cm3, 85% of bulk density) with high dielectric constant of κ=19 and leakage current density of J=2.0×10-6 A/cm2 at -1 MV/cm has been achieved at optimized deposition conditions. Bilayer graphene on HfO2/Si substrate has been successfully identified and also transistor has been fabricated with HfO2 (35 nm) as a back gate. High transconductance compared to other back gated devices such as SiO2/Si and Al2O3/Si and high mobility have been achieved. The performance of back gated bilayer graphene transistors on HfO2 films deposited at two O2 flow rates of 3 SCCM and 20 SCCM has been evaluated. It is found that the device on the film deposited at 3 SCCM O2 flow rate shows better properties. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. MoS2 layers on the optimized HfO2/Si substrate have been successfully identified and transistor has been fabricated with HfO2 (32 nm) as a back gate. The device is switching at lower voltages compared to SiO2 back gated devices with high ION/IOFF ratio (>106). The effect of film thickness on optical, structural, compositional and electrical properties for top gate applications has been studied. Also the effect of gate electrode material and its processing on electrical properties of MOS capacitors have been studied. EOT of 1.2 nm with leakage current density of 1×10-4 A/cm2 at -1V has been achieved.