This study investigates the potential benefits and challenges of using layer 3 Internet Protocol version 6 (IPv6) configuration commands. Although any other type of layers 3 devices could have been used in this study, only Cisco routers and multilayer switches are considered. The study is conducted using a simulator called Graphical Network Simulator-3 (GNS3). Even though real Cisco Internetwork Operating System (IOS) software is reliably used in this simulator, an avoidable limitation of this method involves not using this software on real routers and multilayer switches. However, it has been found that contrary to Cisco documentation, using the outgoing local interface as next hop address causes IPv6 static routing not to work; it only works when the neighbouring global unicast address is used as the next hop address. Other findings show that when static addresses are configured with Routing Information Protocol Next Generation (RIPng), Enhanced Interior Gateway Routing Protocol version 6 (EIGRPv6) or Open Shortest Path First version 3 (OSPFv3), RIPng has the best round-trip time (RTT), while OSPFv3 gives the best traceroute results. Likewise, 64-bit Extended Unique Identifier (EUI-64) addresses produce better RTT and traceroute results with RIPng than with EIGRPv6 and OSPFv3. Nonetheless, one challenge for RIPng involves failure to start the RIPng process by misconfiguring the ipv6 router rip name and ipv6 rip name enable commands. The benefit of EIGRPv6 is that its RTT is faster than that of OSPFv3 and even if the router identifiers (router-ids) are configured the same on all the routers, the EIGRPv6 process still works well. However, configuring different autonomous system numbers and failing to configure the "no shutdown" or router-id commands results in routing challenges. On the other hand, configuring the same router-id on different layer 3 devices causes OSPFv3 not to work. In spite of this challenge, when OSPFv3 is used with Hot Standby Router Protocol version 2 (HSRPv2), it generates faster RTT than EIGRPv6 and RIPng. However, the success rate of OSPFv3 for failover time of the active router to the standby router is 4% lower than EIGRPv6. In comparison to Internet Protocol version 4 (IPv4), configuring of static and EUI-64 address commands is a very challenging task, because of the hexadecimal nature of IPv6 addresses. Despite this challenge, one benefit of these commands is the ability to use slash notation such as /64 for the prefix length. When used on dual stack commands, static addresses give better native router processing performance with no encapsulation overheads. However, configuring these addresses on dual stack commands in large networks is a challenge. With regard to manual IPv6 tunnelling, configuring the tunnel interface addresses in the same network and failure to configure the tunnel mode ipv6ip command, prevents this technique from working. Although IPv6 static Network Address Translation-Protocol Translation (NAT-PT) commands are easy to configure and to troubleshoot, the NAT-PT router raises the challenge of being a single point of failure in the network. On the whole, given these benefits and challenges, implementing IPv6 in industrial networks should not be scary. The results of this study are useful guidelines on how to efficiently design and configure IPv6 networks in a smooth way. / Dissertation (MEng)--University of Pretoria, 2016. / Electrical, Electronic and Computer Engineering / MEng / Unrestricted

This doctoral thesis outlines several methodological advances in network science aimed towards uncovering rapid, complex interdependencies of electromagnetic brain activity recorded from the Electroencephalogram (EEG). This entails both new analyses and modelling of EEG brain network topologies and a novel approach to analyse rapid dynamics of connectivity. Importantly, we implement these advances to provide novel insights into pathological brain function in Alzheimer's disease. We introduce the concept of hierarchical complexity of network topology, providing both an index to measure it and a model to simulate it. We then show that the topology of functional connectivity estimated from EEG recordings is hierarchically complex, existing in a scale between random and star-like topologies, this is a paradigm shift from the established understanding that complexity arises between random and regular topologies. We go on to consider the density appropriate for binarisation of EEG functional connectivity, a methodological step recommended to produce compact and unbiased networks, in light of its new-found hierarchical complexity. Through simulations and real EEG data, we show the benefit of going beyond often recommended sparse representations to account for a broader range of hierarchy level interactions. After this, we turn our attention to assessing dynamic changes in connectivity. By constructing a unified framework for multivariate signals and graphs, inspired by network science and graph signal processing, we introduce graph-variate signal analysis which allows us to capture rapid fluctuations in connectivity robust to spurious short-term correlations. We define this for three pertinent brain connectivity estimates - Pearson's correlation coefficient, coherence and phase-lag index - and show its benefit over standard dynamic connectivity measures in a range of simulations and real data. Applying these novel methods to EEG datasets of the performance of visual short-term memory binding tasks by familial and sporadic Alzheimer's disease patients, we uncover disorganisation of the topological hierarchy of EEG brain function and abnormalities of transient phase-based activity which paves the way for new interpretations of the disease's affect on brain function. Hierarchical complexity and graph-variate dynamic connectivity are entirely new methods for analysing EEG brain networks. The former provides new interpretations of complexity in static connectivity patterns while the latter enables robust analysis of transient temporal connectivity patterns, both at the frontiers of analysis. Although designed with EEG functional connectivity in mind, we hope these techniques will be picked up in the broader field, having consequences for research into complex networks in general.

A demanda por sistemas com elevado desempenho tem trazido a necessidade de aumentar o número de elementos de processamento, surgindo os chamados Sistemas em Chip Multiprocessados (MPSoCs). Além disso, com a possibilidade de redução da escala tecnológica na era submicrônica, permitindo a integração de vários dispositivos, os chips têm se tornado ainda mais complexos. No entanto, com o aumento no número de elementos de processamento, as interconexões são vistas com o principal gargalo dos sistemas-em-chip. Com isso, uma preocupação na forma como tais elementos se comunicam e estão interconectados tem sido levantada, uma vez que tais características são cruciais nos aspectos de desempenho, energia e potência, principalmente em sistemas embarcados. Essa necessidade permitiu o advento das redes-em-chip (Networks-on-Chip – NoCs) e inúmeros estudos já foram realizados para tais dispositivos. No entanto, devido ao aceleramento tecnológico atual, que traz a necessidade por sistemas ainda mais complexos, que consumam baixa energia e que permitam que as aplicações sejam constantemente atualizadas sem perder as características de desempenho, as arquiteturas de interconexão tradicionais não serão suficientes para satisfazer tais desafios. Outras alternativas de interconexão para MPSoCs precisam ser investigadas e nesse trabalho novas arquiteturas para NoCs com tais requisitos são apresentadas. As soluções propostas exploram hierarquia, adaptabilidade e interconexões em três dimensões. Esse trabalho aborda a necessidade do uso de diferentes estratégias em NoCs a fim de atingir os requisitos de desempenho e baixo consumo de potência dos atuais e futuros MPSoCs. Dessa forma, serão verificadas as diversas arquiteturas de interconexões para sistemas heterogêneos, sua escalabilidade, suas principais características e as vantagens das propostas apresentadas sobre as demais soluções. / The demand for systems with high performance has brought the need to increase the number of cores, emerging the called Multi-Processors System-on-Chip (MPSoCs). Also, with the shrinking feature size in deep-submicron era, allowing the integration of several devices, chips have become even more complex. However, with the increase in these elements, interconnections are seen as the main bottleneck in many core systemson- chip. With this, a concern about how these devices communicate and are interconnected has been raised, since these features are crucial for the performance, energy and power consumption aspects, mainly in embedded systems. This need allows the advent of the Networks-on-Chip (NoCs) and countless studies had already been done to analyze such interconnection devices. However, due to the current technological accelerating that brings the need for even more complex systems, consuming lower energy and providing constant application updates without losing performance features, traditional interconnect architectures will not be sufficient to satisfy such challenges. Other interconnecting alternatives for MPSoCs need to be investigated and in this work, novel architectures for NoCs meeting such requirements are presented. The proposed solutions explore hierarchy, adaptability and three dimensional interconnections. This work approaches the requirements in the use of different strategies for NoCs in order to reach the performance requisites and low power consumption of the current and future MPSoCs. Hence, in this approach, several interconnection architectures for heterogeneous systems, their scalability and the main features and advantages of the proposed strategies in comparison with others will be verified.

A demanda por sistemas com elevado desempenho tem trazido a necessidade de aumentar o número de elementos de processamento, surgindo os chamados Sistemas em Chip Multiprocessados (MPSoCs). Além disso, com a possibilidade de redução da escala tecnológica na era submicrônica, permitindo a integração de vários dispositivos, os chips têm se tornado ainda mais complexos. No entanto, com o aumento no número de elementos de processamento, as interconexões são vistas com o principal gargalo dos sistemas-em-chip. Com isso, uma preocupação na forma como tais elementos se comunicam e estão interconectados tem sido levantada, uma vez que tais características são cruciais nos aspectos de desempenho, energia e potência, principalmente em sistemas embarcados. Essa necessidade permitiu o advento das redes-em-chip (Networks-on-Chip – NoCs) e inúmeros estudos já foram realizados para tais dispositivos. No entanto, devido ao aceleramento tecnológico atual, que traz a necessidade por sistemas ainda mais complexos, que consumam baixa energia e que permitam que as aplicações sejam constantemente atualizadas sem perder as características de desempenho, as arquiteturas de interconexão tradicionais não serão suficientes para satisfazer tais desafios. Outras alternativas de interconexão para MPSoCs precisam ser investigadas e nesse trabalho novas arquiteturas para NoCs com tais requisitos são apresentadas. As soluções propostas exploram hierarquia, adaptabilidade e interconexões em três dimensões. Esse trabalho aborda a necessidade do uso de diferentes estratégias em NoCs a fim de atingir os requisitos de desempenho e baixo consumo de potência dos atuais e futuros MPSoCs. Dessa forma, serão verificadas as diversas arquiteturas de interconexões para sistemas heterogêneos, sua escalabilidade, suas principais características e as vantagens das propostas apresentadas sobre as demais soluções. / The demand for systems with high performance has brought the need to increase the number of cores, emerging the called Multi-Processors System-on-Chip (MPSoCs). Also, with the shrinking feature size in deep-submicron era, allowing the integration of several devices, chips have become even more complex. However, with the increase in these elements, interconnections are seen as the main bottleneck in many core systemson- chip. With this, a concern about how these devices communicate and are interconnected has been raised, since these features are crucial for the performance, energy and power consumption aspects, mainly in embedded systems. This need allows the advent of the Networks-on-Chip (NoCs) and countless studies had already been done to analyze such interconnection devices. However, due to the current technological accelerating that brings the need for even more complex systems, consuming lower energy and providing constant application updates without losing performance features, traditional interconnect architectures will not be sufficient to satisfy such challenges. Other interconnecting alternatives for MPSoCs need to be investigated and in this work, novel architectures for NoCs meeting such requirements are presented. The proposed solutions explore hierarchy, adaptability and three dimensional interconnections. This work approaches the requirements in the use of different strategies for NoCs in order to reach the performance requisites and low power consumption of the current and future MPSoCs. Hence, in this approach, several interconnection architectures for heterogeneous systems, their scalability and the main features and advantages of the proposed strategies in comparison with others will be verified.

A demanda por sistemas com elevado desempenho tem trazido a necessidade de aumentar o número de elementos de processamento, surgindo os chamados Sistemas em Chip Multiprocessados (MPSoCs). Além disso, com a possibilidade de redução da escala tecnológica na era submicrônica, permitindo a integração de vários dispositivos, os chips têm se tornado ainda mais complexos. No entanto, com o aumento no número de elementos de processamento, as interconexões são vistas com o principal gargalo dos sistemas-em-chip. Com isso, uma preocupação na forma como tais elementos se comunicam e estão interconectados tem sido levantada, uma vez que tais características são cruciais nos aspectos de desempenho, energia e potência, principalmente em sistemas embarcados. Essa necessidade permitiu o advento das redes-em-chip (Networks-on-Chip – NoCs) e inúmeros estudos já foram realizados para tais dispositivos. No entanto, devido ao aceleramento tecnológico atual, que traz a necessidade por sistemas ainda mais complexos, que consumam baixa energia e que permitam que as aplicações sejam constantemente atualizadas sem perder as características de desempenho, as arquiteturas de interconexão tradicionais não serão suficientes para satisfazer tais desafios. Outras alternativas de interconexão para MPSoCs precisam ser investigadas e nesse trabalho novas arquiteturas para NoCs com tais requisitos são apresentadas. As soluções propostas exploram hierarquia, adaptabilidade e interconexões em três dimensões. Esse trabalho aborda a necessidade do uso de diferentes estratégias em NoCs a fim de atingir os requisitos de desempenho e baixo consumo de potência dos atuais e futuros MPSoCs. Dessa forma, serão verificadas as diversas arquiteturas de interconexões para sistemas heterogêneos, sua escalabilidade, suas principais características e as vantagens das propostas apresentadas sobre as demais soluções. / The demand for systems with high performance has brought the need to increase the number of cores, emerging the called Multi-Processors System-on-Chip (MPSoCs). Also, with the shrinking feature size in deep-submicron era, allowing the integration of several devices, chips have become even more complex. However, with the increase in these elements, interconnections are seen as the main bottleneck in many core systemson- chip. With this, a concern about how these devices communicate and are interconnected has been raised, since these features are crucial for the performance, energy and power consumption aspects, mainly in embedded systems. This need allows the advent of the Networks-on-Chip (NoCs) and countless studies had already been done to analyze such interconnection devices. However, due to the current technological accelerating that brings the need for even more complex systems, consuming lower energy and providing constant application updates without losing performance features, traditional interconnect architectures will not be sufficient to satisfy such challenges. Other interconnecting alternatives for MPSoCs need to be investigated and in this work, novel architectures for NoCs meeting such requirements are presented. The proposed solutions explore hierarchy, adaptability and three dimensional interconnections. This work approaches the requirements in the use of different strategies for NoCs in order to reach the performance requisites and low power consumption of the current and future MPSoCs. Hence, in this approach, several interconnection architectures for heterogeneous systems, their scalability and the main features and advantages of the proposed strategies in comparison with others will be verified.