L'écart de vitesse entre le processeur et la mémoire vive est devenu un point faible pour les performances des systèmes. En raison de ces limitations, de nombreuses mémoires émergentes ont été proposées comme solutions alternatives à ces problèmes existant dans la hiérarchie mémoire. Les mémoires résistives (RRAM) sont considérées comme des candidats pour la « storage class memory » (SCM), les mémoires non volatiles embarquées (eNVM), et les systèmes neuromorphique. Cependant, les problèmes de fiabilité tels que la rétention de données sont encore en cours d'amélioration. De plus, pour obtenir des matrices mémoires de grande densité, la RRAM a besoin des sélecteurs qui seront intégrer en série avec elle dans une architecture un-sélecteur une-résistance (1S1R). Le sélecteur est nécessaire avec le point mémoire pour éliminer les problèmes des courants de fuite, qui gênent le bon fonctionnement de la matrice mémoire dans des architectures crossbar et verticales 3D.Dans cette thèse, notre objectif principal est de traiter les défis ci-dessus. Notre travail peut être divisé en deux parties principales : i) l'étude de la fiabilité des cellules RRAM basées sur HfO2 et ii) la caractérisation des opérations de base et des performances des cellules RRAM basées sur HfO2 et qui sont co-intégrées avec deux types différents des sélecteurs. Pour la partie fiabilité, nous avons étudié les effets du dopage aluminium (Al) sur la rétention de données des cellules RRAM à base de HfO2. Des dispositifs à simple et double couche avec différentes concentrations d'aluminium ont été fabriqués et testés. A partir des comportements électriques macroscopiques, comme la dégradation du diélectrique en fonction du temps (TDDB) et l’opération de forming avec des rampes de tension, on a extrait des propriétés microscopiques des matériaux tels que l'énergie d'activation nécessaire pour la rupture d’une liaison chimique à champ nul et le moment dipolaire des liaisons dans les matériaux testés. En utilisant ces paramètres microscopiques nous avons effectué tout au long de ce travail des simulations physiques pour comprendre les dynamiques de l’opération de forming ainsi que les mécanismes physiques impliqués pendant les opérations du dispositif mémoire. Deuxièmement, nous avons étudié l'immunité aux rayonnements de la RRAM à base de HfO2 pour les applications spatiales. Nos dispositifs RRAM ont été exposés à une énergie de 266 MeV d'ions lourds d'iode. Des analyses pré- et post-exposition ont été effectuées sur les états de la mémoire et les tensions de programmation pour étudier les effets de l'irradiation sur les caractéristiques du dispositif mémoire.Dans la partie des dispositifs d’accès, nous avons évalué deux types différents des sélecteurs. Une forte non-linéarité dans les caractéristiques courant / tension est obligatoire pour effectuer une lecture précise et une écriture à faible consommation. Dans le premier dispositif étudié, la sélectivité est introduite en ajoutant une couche d'oxyde dans l’empilement mémoire et qui agit comme une barrière tunnel. Le principal avantage de cette méthode est la facilité d’intégration de la barrière tunnel, par contre elle souffre d'une faible sélectivité (~ 10) et d'un faible courant de programmation qui dégrade la rétention de données. Deuxièmement, on a co-intégré avec l’RRAM un sélecteur OTS et le dispositif 1S1R a été entièrement caractérisé. Le sélecteur OTS offre une plus grande sélectivité par rapport à la barrière tunnel avec les possibilités d'augmenter fortement cette sélectivité par l'ingénierie des matériaux chalcogénures. Plus de 106 cycles de lecture ont été obtenu pour les dispositifs 1S1R en utilisant une stratégie de lecture innovante que nous avons suggérée pour éviter les lectures perturbatrices et réduire la consommation d'énergie. / The performance gaps in nowadays memory hierarchy on the first hand between processor and main memory, on the other hand between main memory and storage have become a bottleneck for system performances. Due to these limitations, many emerging memories have been proposed as alternative solutions to fill out such concerns. The emerging non-volatile resistive random-access memories (RRAM) are considered as strong candidates for storage class memory (SCM), embedded nonvolatile memories (eNVM), enhanced solid-state disks, and neuromorphic computing. However, reliability challenges such as RRAM thermal stability and resistance variability are still under improvement processes. In addition, to achieve high integration densities the RRAM needs two terminal selector devices in one-selector one-resistor (1S1R) serial cell. The BEOL selector device enables suppression of the parasitic leakage paths, which hinder memory array operation in crossbar and vertical 3D architectures.In this PhD, our main focus is to address and treat the above challenges. Here, the work can be divided into two main parts: i) the investigation of the reliability of HfO2 based RRAM cells and ii) the characterization of the basis memory operations and performances of HfO2 based RRAM cells co-integrated with two different back end of line (BEOL) selector technologies.For the reliability part, we have investigated the effects of aluminum (Al) doping on data retention of HfO2 based RRAM cells. Single and double layer devices with different aluminum concentration were fabricated and tested. From macroscopic electrical characteristics, like time dependent dielectric breakdown (TDDB) and ramped voltage forming, microscopic properties of the materials such as the activation energy to break a bond at zero field and the dipole moment of the bond were extracted. These parameters have been used to shed new light on the mechanisms governing the forming process by means of device level simulations. Second, we have addressed the radiation immunity of HfO2 based RRAM for possible space applications as well. Our RRAM devices were exposed to 266 MeV Iodine heavy ions energy. Pre- and post-exposure analysis were carried out on the memory states and the programming voltages to study the effects of the irradiation on the memory characteristics. Throughout this work, we have performed physics based simulations to understand the dynamics of the forming process as well as the physical mechanisms involved during the memory operations.For the access devices part, we have evaluated two different types of selectors. For accurate reading and low power writing a strong selectivity in the current/voltage characteristics is required. In the first studied device, the selectivity is introduced by adding an oxide tunnel barrier. The main advantage of this strategy is that it is easy to integrate, however it suffers of low selectivity (~10) and low programming current. Second, an OTS based selector co-integrated with HfO2 based RRAM was fully characterized. OTS selector provides higher selectivity compared to the oxide tunnel barrier with the possibilities to strongly increase this selectivity by material engineering. Over 106 read cycles have been achieved on our 1S1R devices using an innovative read strategy that we have suggested to prevent disruptive read and to reduce the power consumption.

Current CMOS-based technologies are facing design challenges related to the continuous scaling down of the minimum feature size, according to Moore’s law. Moreover, conventional computing architecture is no longer an effective way of fulfilling modern applications demands, such as big data analysis, pattern recognition, and vector processing. Therefore, there is an exigent need to shift to new technologies, at both the architecture and the device levels. Recently, memristor devices and structures attracted attention for being promising candidates for this job. Memristor device adds a new dimension for designing novel circuits and systems. In addition, high-density memristor-based crossbar is widely considered to be the essential element for future memory and bio-inspired computing systems. However, numerous challenges need to be addressed before the memristor genuinely replaces current memory and computing technologies, which is the motivation behind this research effort. In order to address the technology challenges, we begin by fabricating and modeling the memristor device. The devices fabricated at our local clean room enriched our understanding of the memristive phenomenon and enabled the experimental testing for our memristor-based circuits. Moreover, our proposed mathematical modeling for memristor behavior is an essential element for the theoretical circuit design stage. Designing and addressing the challenges of memristor systems with practical complexity, however, requires an extra step, which takes the form of a reliable and modular simulation platform. We, therefore, built a new simulation platform for the resistive crossbar, which can simulate realistic size arrays filled with real memory data. In addition, this simulation platform includes various crossbar nonidealities in order to obtain accurate simulation results. Consequently, we were able to address the significant challenges facing the high density memristor crossbar, as the building block for resistive-based memory systems and neural computing. For gateless arrays, we present multiport array structure and readout technique, which for the first time introduces a closed-form solution for the challenging crossbar sneak-paths problem. Moreover, a new adaptive threshold readout methodology is proposed, which employs the memory hierarchy locality property in order to improve the access time to the memristor crossbar. Another fast readout technique based on binary counters is presented for locality-less crossbar systems. On the other hand, for gated arrays, we present new readout technique and circuitry that combines the advantages of the gated and gateless memristor arrays, namely the high-density and low-power consumption. In general, the presented structures and readout methodologies empower much faster and power efficient access to the high-density memristive crossbar, compared to other works presented in the literature. Finally, at the circuit level, we propose novel reactance-less oscillators based on memristor devices, which find promising applications in embedded systems and bio-inspired computing. Altogether, we believe that our contributions to the emerging technology help to push it to the next level, shortening the path towards better futuristic computing systems.

This thesis involves modeling, design, Hardware Description Language (HDL) design capture, synthesis, implementation and HDL virtual prototype simulation validation of an interconnect network for a Hybrid Data/Command Driven Computer Architecture (HDCA) system. The HDCA is a single-chip shared memory multiprocessor architecture system. Various candidate processor-memory interconnect topologies that may meet the requirements of the HDCA system are studied and evaluated related to utilization within the HDCA system. It is determined that the Crossbar network topology best meets the HDCA system requirements and it is therefore used as the processormemory interconnect network of the HDCA system. The design capture, synthesis, implementation and HDL simulation is done in VHDL using XILINX ISE 6.2.3i and ModelSim 5.7g CAD softwares. The design is validated by individually testing against some possible test cases and then integrated into the HDCA system and validated against two different applications. The inclusion of crossbar switch in the HDCA architecture involved major modifications to the HDCA system and some minor changes in the design of the switch. Virtual Prototype testing of the HDCA executing applications when utilizing crossbar interconnect revealed proper functioning of the interconnect and HDCA. Inclusion of the interconnect into the HDCA now allows it to implement dynamic node level reconfigurability and multiple forking functionality.

Nowadays, researchers are trying to shrink the memory cell in order to increase the capacity of the memory system and reduce the hardware costs. In recent years, there has been a revolution in electronics by using fundamentals of physics to build a new memory for computer application in order to increase the capacity and decrease the power consumption. Increasing the capacity of the memory causes a growth in the chip area. From 1971 to 2012 semiconductor manufacturing process improved from 6µm to 22 µm. In May 2008, S.Williams stated that "it is time to stop shrinking". In his paper, he declared that the process of shrinking memory element has recently become very slow and it is time to use another alternative in order to create memory elements [9]. In this project, we present a new design of a memory array using the new element named Memristor [3]. Memristor is a two-terminal passive electrical element that relates the charge and magnetic flux to each other. The device remained unknown since 1971 when it was discovered by Chua and introduced as the fourth fundamental passive element like capacitor, inductor and resistor [3]. Memristor has a dynamic resistance and it can retain its previous value even after disconnecting the power supply. Due to this interesting behavior of the Memristor, it can be a good replacement for all of the Non-Volatile Memories (NVMs) in the near future. Combination of this newly introduced element with the nanowire crossbar architecture would be a great structure which is called Crossbar Memristor. Some frameworks have recently been introduced in literature that utilized Memristor crossbar array, but there are many challenges to implement the Memristor crossbar array due to fabrication and device limitations. In this work, we proposed a simple design of Memristor crossbar array architecture which uses input feedback in order to preserve its data after each read operation

Memristor-based nano-crossbar computing is a revolutionary computing paradigm that does away with the traditional Von Neumann architectural separation of memory and computation units. The computation of Boolean formulas using memristor circuits has been a subject of several recent investigations. Crossbar computing, in general, has also been a topic of active interest, but sneak paths have posed a hurdle in the design of pervasive general-purpose crossbar computing paradigms. In this paper, we demonstrate that sneak paths in nano-crossbar computing can be exploited to design a Boolean-formula evaluation strategy. We demonstrate our approach on a simple Boolean formula and a 1-bit addition circuit. We also conjecture that our nano-crossbar design will be an effective approach for synthesizing high-performance customized arithmetic and logic circuits.

Deep neural networks (DNNs) are receiving immense attention because of their ability to solve complex problems. However, running a DNN requires a very large number of computations. Hence, dedicated hardware optimized for running deep learning algorithms known as neuromorphic architectures is often utilized. This dissertation focuses on evaluating andenhancing the accuracy of these neuromorphic architectures considering the designs of components, process variations, and adversarial attacks. The first contribution of the dissertation (Chapter 2) proposes design enhancements in analog Memristive Crossbar Array(MCA)-based neuromorphic architectures to improve classification accuracy. It introduces an analog Winner-Take-All (WTA) architecture and an on-chip training architecture. WTA ensures that the classification of the analog MCA is correct at the final selection level and the highest probability is selected. In particular, this dissertation presents a design of a highly scalable and precise current-mode WTA circuit with digital address generation. The design is based on current mirrors and comparators that use the cross-coupled latch structure. A post-silicon calibration circuit is also presented to handle process variations. On-chip training ensures that there is consistency in classification accuracy among different all analog MCA-based neuromorphic chips. Finally, an enhancement to the analog on-chip training architecture by implementing the Convolutional Neural Network (CNN) on MCA and software considerations to accelerate the training is presented.The second focus of the dissertation (Chapter 3) is on producing correct classification in the presence of malicious inputs known as adversarial attacks. This dissertation shows that MCA-based neuromorphic architectures ensure correct classification when the input is compromised using existing adversarial attack models. Furthermore, it shows that adversarialrobustness can be further improved by compression-based preprocessing steps that can be implemented on MCAs. It also evaluates the impact of the architecture in Chapter 2 under adversarial attacks. It shows that adversarial attacks do not uniformly affect the classification accuracy of different MCA-based chips. Experimental evidence using a variety of datasets and attack models supports the impact of MCA-based neuromorphic architectures and compression-based preprocessing implemented on MCAs to mitigate adversarial attacks. It is also experimentally shown that the on-chip training improves consistency in mitigating adversarial attacks among different chips. The final contribution (Chapter 4) of this dissertation introduces an enhancement of the method in Chapter 3. It consists of input preprocessing using compression and subsequent rescale and rearrange operations that are implemented using MCAs. This approach further improves the robustness against adversarial attacks. The rescale and rearrange operations are implemented using a DNN consisting of fully connected and convolutional layers. Experimental results show improved defense compared to similar input preprocessing techniques on MCAs.

FPGAs are commonly used in cloud computing due to their ability  to be  programmed  as a processor that serves a specific purpose; hence, achieving high performance at low power. On the other hand, FPGAs have a lot of resources available, which are wasted if they host a single application or serve a single user’s request. Partially Reconfiguration technology enables FPGAs to divide their resources into different regions and then dynamically reprogram those regions with various applications during runtime. Therefore, they are considered as a good solution to eliminate the underutilization resource problem. Nevertheless, the sizes of these regions are static; they cannot be increased or decreased once they are defined. Thereby, it leads to the underutilization of reconfigurable region resources. This thesis addresses this problem, i.e., how to dynamically increase/decrease partially reconfigurable FPGA resources matching an application’s needs. Our solution enables expanding and contracting the FPGA resources allocated to an application by 1) application acceleration requirements expressed in multiple smaller modules which are configured into multiple reconfigurable regions assigned to the application dynamically  and 2) providing a low - area - overhead, configurable, and isolated communication mechanism by adjusting crossbar interconnect and WISHBONE interface among those multiple reconfigurable regions. / FPGA - kretsar har en förmåga  att programmeras som processorer med ett specifikt syfte vilket gör att de ofta används i molnlösningar. Det tager hög prestanda med låg effektförbrukning. Å andra sidan disponerar FPGA - kretsar över stora resurser, vilka är bortkastade om de enbart används av en applikation eller endast på en användares förfrågan. Partiellt omkonfigurerbara teknologier tillåter FPGA - kretsar att fördela resurser mellan olika regioner, och sen dynamiskt omprogrammera regioner med olika applikationer vid körning. Därför betraktas partiellt omkonfigurerbara teknologier som en bra lösning för att minimera underutnyttjande av resurser. Storleken på regionerna är statiska och kan inte ändras när de väl definierats, vilket leder till underutnyttjande av de omkonfigurerbara regionernas resurser. Denna uppsats angriper problemet med dynamisk allokering av partiellt omkonfigurerbara FPGA - resurser utifrån applikationens behov. Vår lösning möjliggör ökning och minskning av FPGA - resurser allokerade till en applikation genom 1) accelerering av applikationen genom att applikationen tilldelas flera mindre moduler konfigurerade till dynamiskt omkonfigurerbara regioner, och 2) tillhanda hållande av en effektiv konfigurerbar och isolerad kommunikationsmekanism, genom justering av crossbar - sammankoppling en  och  WISHBONE - gränssnittet hos de omkonfigurerbara regionerna.

Alors que les mémoires non-volatiles conventionnelles, telles que les mémoires flash à grille flottante, deviennent de plus en plus complexes à intégrer et souffrent de performances et d’une fiabilité de plus en plus réduite, les mémoires à variation de résistance (RRAM) telles que les OxRAM, CBRAM, MRAM ou PCM sont vues dans la communauté scientifique comme une alternative crédible. Cependant, les architectures de RRAM standard (telles que la 1Transistor-1RRAM) ne sont pas compétitives avec les mémoires flash sur le terrain de la densité. Ainsi, cette thèse se propose d’explorer le potentiel des architectures RRAM sans transistor que sont l’architecture Crosspoint et l’architecture VRRAM.Dans un premier temps, le positionnement des architectures Crosspoint et VRRAM dans la hiérarchie mémoire est étudié. De nouvelles problématiques, telles que les courant de sneakpath, la chute de tension dans les métaux ou la surface des circuits périphériques sont identifiées et modélisées. Dans un second temps, des solutions circuit répondant aux problématiques évoquées précédemment sont proposées. Finalement, cette thèse se propose d’explorer les opportunités ouvertes par l’utilisation de transistors innovants pour améliorer la densité ou les performances des architectures mémoires utilisant des RRAM. / While conventional non-volatiles memories, such as floating gate Flash memories, are becoming more and more difficult and costly to integrate and suffer of reduced performances and reliability, emerging resistive switching memories (RRAM), such as OxRAM, CBRAM, MRAM or PCM, are seen in the scientific community as a good way for tomorrow’s high-density memories. However, standard RRAM architectures (such as 1 Transistor-1 RRAM) are not competitive with flash technology in terms of density. Thereby, this thesis proposes to explore the opportunities opened by transistor-less RRAM architectures: Crosspoint and Vertical RRAM (VRRAM) architectures.First, the positioning of Crosspoint and VRRAM architectures in the memory hierarchy is studied. New constraints such as the sneakpath currents, the voltage drop through the metal lines or the periphery area overhead are identified and modeled. In a second time, circuit solutions answering to previously mentioned effects are proposed. Finally, this thesis proposes to explore new opportunities opened by the use of innovative transistors to improve the density or the performances of RRAM-based memory architectures.

Les nouvelles techniques de fabrication nanométriques comme l’auto-assemblage ou la nanoimpression permettent de réaliser des matrices régulières (crossbars) atteignant des densités extrêmes (jusqu’à 1012 nanocomposants/cm2) tout en limitant leur coût de fabrication. Cependant, il est attendu que ces technologies s’accompagnent d’une augmentation significative du nombre de défauts et de dispersions de caractéristiques. La capacité à exploiter ces crossbars est alors conditionnée par le développement de nouvelles techniques de calcul capables de les spécialiser et de tolérer une grande densité de défauts. Dans ce contexte, l’approche neuromimétique qui permet tout à la fois de configurer les nanodispositifs et de tolérer leurs défauts et dispersions de caractéristiques apparaît spécialement pertinente. L’objectif de cette thèse est de démontrer l’efficacité d’une telle approche et de quantifier la fiabilité obtenue avec une architecture neuromimétique à base de crossbar de memristors, ou neurocrossbar (NC). Tout d’abord la thèse introduit des algorithmes permettant l’apprentissage de fonctions logiques sur un NC. Par la suite, la thèse caractérise la tolérance du modèle NC aux défauts et aux variations de caractéristiques des memristors. Des modèles analytiques probabilistes de prédiction de la convergence de NC ont été proposés et confrontés à des simulations Monte-Carlo. Ils prennent en compte l’impact de chaque type de défaut et de dispersion. Grâce à ces modèles analytiques il devient possible d’extrapoler cette étude à des circuits NC de très grande taille. Finalement, l’efficacité des méthodes proposées est expérimentalement démontrée à travers l’apprentissage de fonctions logiques par un NC composé de transistors à nanotube de carbone à commande optique (OG-CNTFET). / Novel manufacturing techniques, such as nanoscale self-assembly or nanoimprint, allow a cost-efficient way to fabricate high-density crossbar matrices (1012 nanodevices/cm2). However, it is expected that these technologies will be accompanied by a significant increase of defects and dispersion in device characteristics. Thus, programming these crossbars require new computational techniques that possess high tolerance for such variations. In this context, approaches based on neural networks are promising for configuring nanodevices, since they provide a natural way for tolerating low yields and device variations. The main objective of this thesis is to explore such a neural-network approach, by examining factors such as efficiency and reliability, using the memristor crossbar architecture or neurocrossbar (NC). We introduce algorithms for learning the logic functions on the NC, and the tolerance of NC against static defects (stuck-defect) and dispersion of device properties is discussed. Probabilistic analytical models for predicting the convergence of NC are proposed and compared with Monte Carlo simulations, which take into account the impact of each type of defect and dispersion. These analytical models can be extrapolated to study large-sized NCs. Finally, the effectiveness of the proposed methods is experimentally demonstrated through the learning of logic functions by a real NC made of Optically Gated Carbon Nanotube Field Effect Transistor (OG-CNTFET).

Multi-Processor System-on-Chip (MPSoC) possui vários processadores, em um único chip. Várias aplicações podem ser executadas de maneira paralela ou uma aplicação paralelizável pode ser particionada e alocada em cada processador, a fim de acelerar a sua execução. Um problema em MPSoCs é a comunicação entre os processadores, necessária para a execução destas aplicações. Neste trabalho, propomos uma arquitetura de rede de interconexão baseada na topologia crossbar, com memória compartilhada. Esta arquitetura é parametrizável, possuindo N processadores e N módulos de memórias. A troca de informação entre os processadores é feita via memória compartilhada. Neste tipo de implementação cada processador executa a sua aplicação em seu próprio módulo de memória. Através da rede, todos os processadores têm completo acesso a seus módulos de memória simultaneamente, permitindo que cada aplicação seja executada concorrentemente. Além disso, um processador pode acessar outros módulos de memória, sempre que necessite obter dados gerados por outro processador. A arquitetura proposta é modelada em VHDL e seu desempenho é analisado através da execução paralela de uma aplicação, em comparação à sua respectiva execução sequencial. A aplicação escolhida consiste na otimização de funções objetivo através do método de Otimização por Enxame de Partículas (Particle Swarm Optimization - PSO). Neste método, um enxame de partículas é distribuído igualmente entre os processadores da rede e, ao final de cada interação, um processador acessa o módulo de memória de outro processador, a fim de obter a melhor posição encontrada pelo enxame alocado neste. A comunicação entre processadores é baseada em três estratégias: anel, vizinhança e broadcast. Essa aplicação foi escolhida por ser computacionalmente intensiva e, dessa forma, uma forte candidata a paralelização. / Multi-Processor System-on-Chip (MPSoC) has multiple processors in a single chip. Multiple applications can be executed in parallel or a parallelizable application can be partitioned and allocated to each processor in order to accelerate their execution. One problem in MPSoCs is the communication between the processors required to implement these applications. In this work, we propose the architecture of an interconnection network based on the crossbar topology, with shared memory. This architecture is parameterizable, having N processors and N memory modules. The exchange of information between processors is done via shared memory. In this type of implementation each processor executes its application stored in its own memory module. Through the network, all processors have complete access to their own memory modules simultaneously allowing each application to run concurrently. Moreover, a processor can access other memory modules, whenever it needs to retrieve data generated by another processor. The proposed architecture is modelled in VHDL and its performance is analysed by the execution of a parallel aplication, in comparison to its sequencial one. The chosen application consists of optimizing some objetive functions by using the Particle Swarm Optimization method. In this method, particles of a swarm are distributed among the processors and, at the end of each iteration, a processor accesses the memory module of another one in order to obtain the best position found in the swarm. The communication between processors is based on three strategies: ring, neighbourhood and broadcast. This application was chosen due to its computational intensive characteristic and, therefore, a strong candidate for parallelization.