abstract: In the era of artificial intelligent (AI), deep neural networks (DNN) have achieved accuracy on par with humans on a variety of recognition tasks. However, the high computation and storage requirement of DNN training and inference have posed challenges to deploying or locally training the DNNs on mobile and wearable devices. Energy-efficient hardware innovation from circuit to architecture level is required.In this dissertation, a smart electrocardiogram (ECG) processor is first presented for ECG-based authentication as well as cardiac monitoring. The 65nm testchip consumes 1.06 μW at 0.55 V for real-time ECG authentication achieving equal error rate of 1.7% for authentication on an in-house 645-subject database. Next, a couple of SRAM-based in-memory computing (IMC) accelerators for deep learning algorithms are presented. Two single-array macros titled XNOR-SRAM and C3SRAM are based on resistive and capacitive networks for XNOR-ACcumulation (XAC) operations, respectively. XNOR-SRAM and C3SRAM macros in 65nm CMOS achieve energy efficiency of 403 TOPS/W and 672 TOPS/W, respectively. Built on top of these two single-array macro designs, two multi-array architectures are presented. The XNOR-SRAM based architecture titled “Vesti” is designed to support configurable multibit activations and large-scale DNNs seamlessly. Vesti employs double-buffering with two groups of in-memory computing SRAMs, effectively hiding the write latency of IMC SRAMs. The Vesti accelerator in 65nm CMOS achieves energy consumption of <20 nJ for MNIST classification and <40μJ for CIFAR-10 classification at 1.0 V supply. More recently, a programmable IMC accelerator (PIMCA) integrating 108 C3SRAM macros of a total size of 3.4 Mb is proposed. The28nm prototype chip achieves system-level energy efficiency of 437/62 TOPS/W at 40 MHz, 1 V supply for DNNs with 1b/2b precision. In addition to the IMC works, this dissertation also presents a convolutional neural network (CNN) learning processor, which accelerates the stochastic gradient descent (SGD) with momentum based training algorithm in 16-bit fixed-point precision. The65nm CNN learning processor achieves peak energy efficiency of 2.6 TOPS/W for16-bit fixed-point operations, consuming 10.45 mW at 0.55 V. In summary, in this dissertation, several hardware innovations from circuit to architecture level are presented, exploiting the reduced algorithm complexity with pruning and low-precision quantization techniques. In particular, macro-level and system-level SRAM based IMC works presented in this dissertation show that SRAM based IMC is one of the promising solutions for energy-efficient intelligent systems. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

Les nouvelles techniques de fabrication nanométriques comme l’auto-assemblage ou la nanoimpression permettent de réaliser des matrices régulières (crossbars) atteignant des densités extrêmes (jusqu’à 1012 nanocomposants/cm2) tout en limitant leur coût de fabrication. Cependant, il est attendu que ces technologies s’accompagnent d’une augmentation significative du nombre de défauts et de dispersions de caractéristiques. La capacité à exploiter ces crossbars est alors conditionnée par le développement de nouvelles techniques de calcul capables de les spécialiser et de tolérer une grande densité de défauts. Dans ce contexte, l’approche neuromimétique qui permet tout à la fois de configurer les nanodispositifs et de tolérer leurs défauts et dispersions de caractéristiques apparaît spécialement pertinente. L’objectif de cette thèse est de démontrer l’efficacité d’une telle approche et de quantifier la fiabilité obtenue avec une architecture neuromimétique à base de crossbar de memristors, ou neurocrossbar (NC). Tout d’abord la thèse introduit des algorithmes permettant l’apprentissage de fonctions logiques sur un NC. Par la suite, la thèse caractérise la tolérance du modèle NC aux défauts et aux variations de caractéristiques des memristors. Des modèles analytiques probabilistes de prédiction de la convergence de NC ont été proposés et confrontés à des simulations Monte-Carlo. Ils prennent en compte l’impact de chaque type de défaut et de dispersion. Grâce à ces modèles analytiques il devient possible d’extrapoler cette étude à des circuits NC de très grande taille. Finalement, l’efficacité des méthodes proposées est expérimentalement démontrée à travers l’apprentissage de fonctions logiques par un NC composé de transistors à nanotube de carbone à commande optique (OG-CNTFET). / Novel manufacturing techniques, such as nanoscale self-assembly or nanoimprint, allow a cost-efficient way to fabricate high-density crossbar matrices (1012 nanodevices/cm2). However, it is expected that these technologies will be accompanied by a significant increase of defects and dispersion in device characteristics. Thus, programming these crossbars require new computational techniques that possess high tolerance for such variations. In this context, approaches based on neural networks are promising for configuring nanodevices, since they provide a natural way for tolerating low yields and device variations. The main objective of this thesis is to explore such a neural-network approach, by examining factors such as efficiency and reliability, using the memristor crossbar architecture or neurocrossbar (NC). We introduce algorithms for learning the logic functions on the NC, and the tolerance of NC against static defects (stuck-defect) and dispersion of device properties is discussed. Probabilistic analytical models for predicting the convergence of NC are proposed and compared with Monte Carlo simulations, which take into account the impact of each type of defect and dispersion. These analytical models can be extrapolated to study large-sized NCs. Finally, the effectiveness of the proposed methods is experimentally demonstrated through the learning of logic functions by a real NC made of Optically Gated Carbon Nanotube Field Effect Transistor (OG-CNTFET).

The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..

<p>Beta-gallium oxide (<i>β</i>-Ga₂O₃) is an emerging wide bandgap semiconductor for next generation power devices which offers the potential to replace GaN and SiC. It has an ultra-wide bandgap (UWBG) of 4.8 eV and a corresponding <i>E</i>_brof 8 MV/cm. <i>β</i>-Ga₂O₃also possesses a decent intrinsic electron mobility limit of 250 cm²/V<i>·</i>s, yielding high Baliga’s figure of merit of 3444. In addition, the large bandgap of <i>β</i>-Ga₂O₃gives stability in harsh environment operation at high temperatures. </p> <p>Although low-cost large-size <i>β</i>-Ga₂O₃native bulk substrates can be realized by melt growth methods, the unique property that (100) surface of <i>β</i>-Ga₂O₃has a large lattice constant of 12.23 Å allows it to be cleaved easily into thin and long nano-membranes. Therefore, <i>β</i>-Ga₂O₃FETs on foreign substrates by transferring can be fabricated and investigated before <i>β</i>-Ga₂O₃epitaxy technology becomes mature and economical viable. Moreover, integrating <i>β</i>-Ga₂O₃on high thermal conductivity materials has an advantage in terms of suppressing self-heating effects. </p><p>In this dissertation, structural and material innovations to overcome and improve critical challenges are summarized as follows: 1) Top-gate nano-membrane <i>β</i>-Ga₂O₃FETs on a high thermal conductivity diamond substrate with record high maximum drain current densities are demonstrated. The reduced self-heating effect due to high thermal conductivity of the substrate was verified by thermoreflectance measurement. 2) Local electro-thermal effect by electrical bias was applied to enhance the electrical performance of devices and improvements of electrical properties were shown after the annealing. 3) Thin thermal bridge materials such as HfO₂and ZrO₂were inserted between <i>β</i>-Ga₂O₃and a sapphire substrate to reduce self heating effects without using a diamond substrate. The improved thermal performance of the device was analyzed by phonon density of states plots of <i>β</i>-Ga₂O₃and the thin film materials. 4) Nano-membrane tri-gate <i>β</i>-Ga₂O₃FETs on SiO₂/Si substrate fabricated via exfoliation have been demonstrated for the first time. 5) Using the robustness of <i>β</i>-Ga₂O₃in harsh environments, <i>β</i>-Ga₂O₃ferroelectric FETs operating as synaptic devices up to 400 °C were demonstrated. The result offers the potential to use the novel device for ultra-wide bandgap logic applications, specifically neuromorphic computing exposed to harsh environments.<br></p>