Dynamic partial reconfiguration of FPGAs allows systems to autonomously alter sections of their design during runtime based on the state of the system. This functionality provides size, weight, and power benefits that are useful in extreme environments such as space. Therefore, NASA has requested research into the feasibility of using a commercial off-the-shelf software flow to convert a static HDL design to support partial reconfiguration. This project presents an analysis of this conversion process using the Xilinx Partial Reconfiguration Flow to convert the static design for the ITU G.729 Voice Decoder. This paper explores the design modifications that must be made to allow for partial reconfiguration. Furthermore, an in-depth description of how to set up the hardware platform to support the HDL application is provided. Finally, timing and size data are presented and analyzed to empirically show the benefits and limitations of using dynamic partial reconfiguration.

Modern Field-Programmable Gate Arrays (FPGAs) are no longer used to implement small “glue logic” circuitries. The high-density of reconfigurable logic resources in today’s FPGAs enable the implementation of large systems in a single chip. FPGAs are highly flexible devices; their functionality can be altered by simply loading a new binary file in their configuration memory. While the flexibility of FPGAs is comparable to General-Purpose Processors (GPPs), in the sense that different functions can be performed using the same hardware, the performance gain that can be achieved using FPGAs can be orders of magnitudes higher as FPGAs offer the ability for customisation of parallel computational architectures. Dynamic Partial Reconfiguration (DPR) allows for changing the functionality of certain blocks on the chip while the rest of the FPGA is operational. DPR has sparked the interest of researchers to explore new computational platforms where computational tasks are off-loaded from a main CPU to be executed using dedicated reconfigurable hardware accelerators configured on demand at run-time. By having a battery of custom accelerators which can be swapped in and out of the FPGA at runtime, a higher computational density can be achieved compared to static systems where the accelerators are bound to fixed locations within the chip. Furthermore, the ability of relocating these accelerators across several locations on the chip allows for the implementation of adaptive systems which can mitigate emerging faults in the FPGA chip when operating in harsh environments. By porting the appropriate fault mitigation techniques in such computational platforms, the advantages of FPGAs can be harnessed in different applications in space and military electronics where FPGAs are usually seen as unreliable devices due to their sensitivity to radiation and extreme environmental conditions. In light of the above, this thesis investigates the deployment of DPR as: 1) a method for enhancing performance by efficient exploitation of the FPGA resources, and 2) a method for enhancing the reliability of systems intended to operate in harsh environments. Achieving optimal performance in such systems requires an efficient internal configuration management system to manage the reconfiguration and execution of the reconfigurable modules in the FPGA. In addition, the system needs to support “fault-resilience” features by integrating parameterisable fault detection and recovery capabilities to meet the reliability standard of fault-tolerant applications. This thesis addresses all the design and implementation aspects of an Internal Configuration Manger (ICM) which supports a novel bitstream relocation model to enable the placement of relocatable accelerators across several locations on the FPGA chip. In addition to supporting all the configuration capabilities required to implement a Reconfigurable Operating System (ROS), the proposed ICM also supports the novel multiple-clone configuration technique which allows for cloning several instances of the same hardware accelerator at the same time resulting in much shorter configuration time compared to traditional configuration techniques. A faulttolerant (FT) version of the proposed ICM which supports a comprehensive faultrecovery scheme is also introduced in this thesis. The proposed FT-ICM is designed with a much smaller area footprint compared to Triple Modular Redundancy (TMR) hardening techniques while keeping a comparable level of fault-resilience. The capabilities of the proposed ICM system are demonstrated with two novel applications. The first application demonstrates a proof-of-concept reliable FPGA server solution used for executing encryption/decryption queries. The proposed server deploys bitstream relocation and modular redundancy to mitigate both permanent and transient faults in the device. It also deploys a novel Built-In Self- Test (BIST) diagnosis scheme, specifically designed to detect emerging permanent faults in the system at run-time. The second application is a data mining application where DPR is used to increase the computational density of a system used to implement the Frequent Itemset Mining (FIM) problem.

FPGA design implementation and debug tools have not kept pace with the advances in FPGA device density. The emphasis on area optimization and circuit speed has resulted in longer runtimes of the implementation tools. We address the implementation problem using a divide-and-conquer approach in which some device area and circuit speed is sacrificed for improved implementation turnaround time. The PATIS floorplanner enables dynamic modular design that accelerates implementation for incremental changes to a design. While the existing implementation flows facilitate timing closure late in the design cycle by reusing the layout of unmodified blocks, dynamic modular design accelerates implementation by achieving timing closure for each block independently. A complete re-implementation is still rapid as the design blocks can be processed by independent and concurrent invocations of the standard tools. PATIS creates the floorplan for implementing modules in the design. Bus macros serve as module interfaces and enable independent implementation of the modules. The dynamic modular design flow achieves around 10x speedup over the standard design flow for our benchmark designs. / Master of Science

Demands on modern computing are becoming more intensive. Keeping up with these demands has increasing complexity. Moore's Law is in decline. Increasing the number of cores on a device has diminishing returns. Specialised architectures provide more efficient and higher performing processors. However, it is not always practical to include every architecture on every device. Running non-native tasks on architectures often results in a drop in performance. This research examines the benefits and limitations of Field Programmable Gate Arrays - Systems on Chip (FPGA-SoC) devices to provide flexible hardware accelerators for heterogeneous architectures. A number of topics are covered, including hardware acceleration of floating-point mathematical functions, dynamic reconfiguration and high-level synthesis. A number of case studies are presented. Dynamic reconfiguration is used to change the configuration of the FPGA at runtime, allowing the hardware accelerators to be changed depending on the current processor tasks. Changing accelerators at runtime has limitations, such as data perturbation. Context switching techniques are applied to the hardware to prevent loss of data and enable de-fragmentation of the FPGA. High level synthesis techniques are used in conjunction with the presented hardware accelerators to synthesise high-level languages into hardware descriptions with optimisations. Techniques for runtime synthesis of hardware accelerators are presented. These can be combined with dynamic reconfiguration to configure FPGAs with appropriate hardware accelerators from a high-level language at runtime. The research demonstrates that FPGA-SoC devices have the potential for providing reconfigurable accelerators for processors in heterogeneous architectures. Metrics show that the FPGA configurations can perform better than other commercial processors. It was demonstrated that it is possible to context switch hardware at runtime, meaning the most can be made of the FPGA-SoC at all times, even as situations change. However, there are many limitations that still need to be overcome, such as management of the implemented hardware, synthesis of new hardware at runtime, reconfiguration times, interfacing of hardware with software and the design of hardware accelerators.

<p>Reconfigurable computing is an old concept that during the past couple of decades has become increasingly popular. The concept combines the flexibility of software with the performance of hardware. One important contributing factor to the uprising in popularity is the presence of FPGAs (field-programmable gate arrays), which realize the concept by allowing the hardware to be reconfigured dynamically. The current state of reconfigurable computing is discussed further in the thesis.</p><p>Debugging is a vital part in the development of a hardware design. It can be done in several ways depending on the situation. The most common way is to perform simulations but in some cases the fault-finding has to be done when the design is implemented in hardware.</p><p>In this thesis a framework concept is designed that utilizes and evaluates some of the reconfigurable computing ideas. The framework provides debugging possibilities for FPGA designs in a novel way, with a modular system where each module provide means to aid finding a specific fault. The framework is added to an existing design, and offers the user a glimpse into the design behavior and the hardware it runs on.</p><p>One of the debug modules will be released separately under a free license. It allows the developer to see the contents of the memories in a design without requiring special debugging equipment.</p>

Reconfigurable computing is an old concept that during the past couple of decades has become increasingly popular. The concept combines the flexibility of software with the performance of hardware. One important contributing factor to the uprising in popularity is the presence of FPGAs (field-programmable gate arrays), which realize the concept by allowing the hardware to be reconfigured dynamically. The current state of reconfigurable computing is discussed further in the thesis. Debugging is a vital part in the development of a hardware design. It can be done in several ways depending on the situation. The most common way is to perform simulations but in some cases the fault-finding has to be done when the design is implemented in hardware. In this thesis a framework concept is designed that utilizes and evaluates some of the reconfigurable computing ideas. The framework provides debugging possibilities for FPGA designs in a novel way, with a modular system where each module provide means to aid finding a specific fault. The framework is added to an existing design, and offers the user a glimpse into the design behavior and the hardware it runs on. One of the debug modules will be released separately under a free license. It allows the developer to see the contents of the memories in a design without requiring special debugging equipment.

Partial Reconfigurable FPGA provides ability of reconfigure the FPGA duringrun-time. But the reconfigurable part is disabled while performing reconfiguration. In order to maintain the functionality of system, data stream should be hold for RP during that time. Due to this feature, the reconfiguration time becomes critical to designed system. Therefore this thesis aims to build a functional partial reconfigurable system and figure out how much time the reconfiguration takes. A XILINX ML605 evaluation board is used for implementing the system, which has one static part and two partial reconfigurable modules, ICMP and HTTP. A Web Client sends different packets to the system requesting different services. These packets’ type information are analyzed and the requests are held by a MicroBlaze core, which also triggers the system’s self-reconfiguration. The reconfiguration swaps the system between ICMP and HTTP modules to handle the requests. Therefore, the reconfiguration time is defined between detection of packet type and completion of reconfiguration. A counter is built in SP for measuring the reconfiguration time. Verification shows that this system works correctly. Analyze of test results indicates that reconfiguration takes 231ms and consumes 9274KB of storage, which saves 93% of time and 50% of storage compared with static FPGA configuration.

In the past two decades, FPGA has been witnessed from its restricted use as glue logic towards real System-on-Chip (SoC) platforms. Profiting from the great development on semiconductor and IC technologies, the programmability of FPGAs enables themselves wide adoption in all kinds of aspects of embedded designs. Modern FPGAs provide the additional capability of being dynamically and partially reconfigured during the system run-time. The run-time reconfigurability enhances FPGA designs from the sole spatial to both spatial and temporal parallelism, providing more design flexibility for advanced system features. Adaptive computing delegates an advanced computing paradigm in which computation tasks and resources are intelligently managed in correspondence with conditional requirements. In this thesis, we investigate adaptive designs on FPGA platforms: We present a comprehensive and practical design framework for adaptive computing based on the FPGA run-time reconfigurability. It concerns several design key issues in different hardware/software layers, specifically hardware architecture, run-time reconfiguration technical support, OS and device drivers, hardware process scheduler, context switching as well as Inter-Process Communications (IPC). Targeting a special application of data acquisition (DAQ) and trigger systems in nuclear and particle physics experiments, we set up the data streaming model and conduct theoretical analysis on the adaptive system. Three application studies are employed to verify the proposed adaptive design framework: The first application demonstrates a peripheral controller adaptable system aiming at general embedded designs. Through dynamically loading/unloading a NOR flash memory controller and an SRAM controller, both flash memory and SRAM accesses may be accomplished with less resource consumption than in traditional static designs. In the second case, two real algorithm processing engines are adaptively time-multiplexed in the same reconfigurable slot for particle recognition computation. Experimental results reveal the reduced on-chip resource requirements, as well as an approximate processing capability of the peer static design. Taking advantage of the FPGA dynamic reconfigurability, we present in the third application a novel on-FPGA interconnection microarchitecture named RouterLess NoC (RL-NoC). RL-NoC employs the novel design concept of Move Logic Not Data (MLND), and significantly distinguishes itself from the existing interconnection architectures such as buses, crossbars or NoCs. It does not rely on routers to deliver packets hop by hop as canonical NoCs do, but buffers data packets in virtual channels and brings various nodes using run-time reconfiguration to produce or consume them. In comparison with canonical packet-switching NoCs, the routerless architecture features lower design complexity, less resource consumption, higher work frequency, more efficient power dissipation as well as comparable or even higher packet delivery efficiency. It is regarded as a promising interconnection approach in some design scenarios on FPGAs, especially for light-weight applications. / QC 20110531

This project investigates a self-reconfiguring rSoC (reconfigurable System on Chip) system which automatically and dynamically loads peripheral controllers, based on the peripherals connected to the system. The Xilinx Virtex-II FGPA, which supports dynamic partial reconfiguration, is used as the experimental target. To implement the system, three main areas are investigated: the peripheral auto detection, the dynamic partial reconfiguration mechanism on the FPGA, and the supporting software. The system core is designed as two defined areas on a single FPGA chip. A fixed area is used for the constant logic circuits (such as soft-core CPU) and partial reconfiguration (PR) slots are used for changeable peripheral controllers. The autoconfiguration process involves three different steps: peripheral auto detection, loading of a peripheral hardware interface configuration, and loading of a peripheral software driver. In our system, we successfully implement the mechanism of peripheral dynamic loading on the rSoC system. Four novel features are provided in the system: 1) Peripheral auto detection. Peripheral boards are automatically detected by the system when connected to the system. 2) Peripheral controller hardware bitstream and software driver dynamic loading. The required peripheral controller hardware bitstream for the connected peripheral board is automatically searched for and loaded by the operating system, as well as the required software driver. Manual operations on these processes are also supported. 3) Individual interface to external environment. Each PR slot provides individual interface to peripheral boards. It is configured by each peripheral controller for board-specific connection. 4) The existing system is extensible. The partial reconfiguration mechanism provided in this project supports at least two PR slots. On higher capacity FPGAs, the number of PR slots could be increased. In our existing system, the time used for the dynamic partial reconfiguration process, including the hardware bitstream loading and the software driver loading, is in the order of 10-20ms, which is an insignificant fraction of the Linux boot time.

Circuit designs for field-programmable gate arrays (FPGAs) are typically compiled by FPGA vendor tools, such as Xilinx's Vivado Design Suite. In recent years, partial reconfiguration (PR) has emerged as a popular technique that allows portions of an FPGA to be dynamically reconfigured after the complete device has been configured with an initial bitstream. However, the nature of current FPGA vendor tools limits further innovation and possible usage models of PR.This thesis presents Maverick, an open-source proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target PR regions in FPGA designs. Maverick builds upon existing open source tools (Yosys, RapidSmith2, and Project X-Ray) to form an end-to-end compilation flow. After an initial static design and PR region are created with Xilinx's Vivado PR flow, Maverick can then compile and configure RMs onto that PR region-without the use of vendor tools. In addition, this work enables users to import and export RMs between Vivado and RapidSmith2.Furthermore, this thesis demonstrates Maverick compiling RMs on both a desktop computer and on the embedded PYNQ-Z1 board, which contains a Zynq 7020 system on chip (SoC). Maverick runs on the ARM processor embedded within the processing system (PS) of the Zynq device, generating partial bitstreams which can then be configured onto a PR region within the programmable logic (PL) fabric of the same Zynq device. This unique case, not possible with current vendor tools like Vivado, demonstrates the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.