Despite the abundance of renewable energy resources, a lack of economically feasible storage solutions for addressing intermittency remains a barrier to advancing their widespread adoption. Reversible solid oxide cells, which can store hydrogen during periods of renewable energy overproduction, have demonstrated potential for grid stabilization applications given their high potential efficiencies and power densities. However, to become economically competitive, improvements to reversible solid oxide cell performance stability and lifetimes are required. This research focuses on understanding the relationship between microstructure and performance in solid oxide cells and explores avenues for mitigating electrode polarization and degradation. Connections between microstructure and performance were first considered in Ni/YSZ symmetric cells, where the relationship between reaction site density and performance was quantified in nanocatalyst-infiltrated cells using EIS, SEM and FIB/SEM 3-D reconstruction. In Ni-infiltrated electrodes, results showed that both increased triple phase boundary density and decreased reaction rate constants contribute to lowering electrode polarization at intermediate temperatures. In electrodes infiltrated with GDC, a mixed ionic/electronic conducting material, reactions can take place on the GDC surface, greatly decreasing electrode polarization. Calculations considering the performance of baseline and GDC-infiltrated electrodes indicated that reactions take place up to 84nm from triple phase boundaries on nickel scaffold particle surfaces. Microstructure/performance relationships were also examined in full cells tested for 500h under electrolysis or reversible conditions; the fuel and oxygen electrodes were characterized with methods including low-voltage SEM, FIB/SEM 3-D reconstruction, and TEM. In both scenarios, the oxygen electrode was shown to contribute minimally to cell degradation. In the fuel electrode, degradation was mainly precipitated by Ni coarsening and loss of active sites; however, these were mitigated during reversible testing by 9% and 8% respectively compared to electrolysis-tested cells. Finally, strategies are discussed for mitigating long-term degradation. To further stabilize reversible full cells, GDC infiltration into the fuel electrode and adjustments to oxygen electrode phase compositions to prevent long-term decomposition are suggested. On the SOC system level, ALD spinel coatings for interconnect materials are considered. To this end, a successful ALD coating process for manganese oxide on stainless steel is discussed.

Parmi les cibles architecturales susceptibles d'être utilisées pour réaliser un système de traitement sur puce (SoC), les architectures reconfigurables dynamiquement (ARD) offrent un potentiel de flexibilité et de dynamicité intéressant. Cependant ce potentiel est encore difficile à exploiter pour réaliser des applications massivement parallèles sur puce. Dans nos travaux nous avons recensé et analysé les solutions actuellement proposées pour utiliser les ARD et nous avons constaté leurs limites parmi lesquelles : l'utilisation d'une technologie particulière ou d'architecture propriétaire, l'absence de prise en compte des applications parallèles, le passage à l'échelle difficile, l'absence de langage adopté par la communauté pour l'utilisation de la flexibilité des ARD, ...Pour déployer une application sur une ARD il est nécessaire de considérer l'hétérogénéité et la dynamicité de l'architecture matérielle d'une part et la parallélisation des traitements d'autre part. L'hétérogénéité permet d'avoir une architecture de traitement adaptée aux besoins fonctionnels de l'application. La dynamicité permet de prendre en compte la dépendance des applications au contexte et de la nature des données. Finalement, une application est naturellement parallèle.Dans nos travaux nous proposons une solution pour le déploiement sur une ARD d'une application parallèle en utilisant les flots de conception standard des SoC. Cette solution est appelée MATIP (MPI Application Task Integreation Platform) et utilise des primitives du standard MPI version 2 pour effectuer les communications et reconfigurer l'architecture de traitement. MATIP est une solution de déploiement au niveau de la conception basée plate-forme (PBD).La plateforme MATIP est modélisée en trois couches : interconnexion, communication et application. Nous avons conçu chaque couche pour que l'ensemble satisfasse les besoins en hétérogénéité et dynamicité des applications parallèles . Pour cela MATIP utilise une architecture à mémoire distribuée et exploite le paradigme de programmation parallèle par passage de message qui favorise le passage à l'échelle de la plateforme.MATIP facilite le déploiement d'une application parallèle sur puce à travers un template en langage Vhdl d'intégration de tâches. L'utilisation des primitives de communication se fait en invoquant des procédures Vhdl.MATIP libère le concepteur de tous les détails liés à l'interconnexion, la communication entre les tâches et à la gestion de la reconfiguration dynamique de la cible matérielle. Un démonstrateur de MATIP a été réalisée sur des FPGA Xilinx à travers la mise en oe{}uvre d'une application constituée de deux tâches statiques et deux tâches dynamiques. MATIP offre une bande passante de 2,4 Gb/s et une la latence pour le transfert d'un octet de 3,43 µs ce qui comparée à d'autres plateformes MPI (TMD-MPI, SOC-MPI, MPI HAL) met MATIP à l'état de l'art. / Among the architectural targets that could be buid a system on chip (SoC), dynamically reconfigurable architectures (DRA) offer interesting potential for flexibility and dynamicity . However this potential is still difficult to use in massively parallel on chip applications. In our work we identified and analyzed the solutions currently proposed to use DRA and found their limitations including: the use of a particular technology or proprietary architecture, the lack of parallel applications consideration, the difficult scalability, the lack of a common language adopted by the community to use the flexibility of DRA ...In our work we propose a solution for deployment on an DRA of a parallel application using standard SoC design flows. This solution is called MATIP ( textit {MPI Application Platform Task Integreation}) and uses primitives of MPI standard Version 2 to make communications and to reconfigure the MP-RSoC architecture . MATIP is a Platform-Based Design (PBD) level solution.The MATIP platform is modeled in three layers: interconnection, communication and application. Each layer is designed to satisfies the requirements of heterogeneity and dynamicity of parallel applications. For this, MATIP uses a distributed memory architecture and utilizes the message passing parallel programming paradigm to enhance scalability of the platform.MATIP frees the designer of all the details related to interconnection, communication between tasks and management of dynamic reconfiguration of the hardware target. A demonstrator of MATIP was performed on Xilinx FPGA through the implementation of an application consisting of two static and two dynamic hardware tasks. MATIP offers a bandwidth of 2.4 Gb / s and latency of 3.43 microseconds for the transfer of a byte. Compared to other MPI platforms (TMD-MPI, SOC-MPI MPI HAL), MATIP is in the state of the art.

This project investigates a self-reconfiguring rSoC (reconfigurable System on Chip) system which automatically and dynamically loads peripheral controllers, based on the peripherals connected to the system. The Xilinx Virtex-II FGPA, which supports dynamic partial reconfiguration, is used as the experimental target. To implement the system, three main areas are investigated: the peripheral auto detection, the dynamic partial reconfiguration mechanism on the FPGA, and the supporting software. The system core is designed as two defined areas on a single FPGA chip. A fixed area is used for the constant logic circuits (such as soft-core CPU) and partial reconfiguration (PR) slots are used for changeable peripheral controllers. The autoconfiguration process involves three different steps: peripheral auto detection, loading of a peripheral hardware interface configuration, and loading of a peripheral software driver. In our system, we successfully implement the mechanism of peripheral dynamic loading on the rSoC system. Four novel features are provided in the system: 1) Peripheral auto detection. Peripheral boards are automatically detected by the system when connected to the system. 2) Peripheral controller hardware bitstream and software driver dynamic loading. The required peripheral controller hardware bitstream for the connected peripheral board is automatically searched for and loaded by the operating system, as well as the required software driver. Manual operations on these processes are also supported. 3) Individual interface to external environment. Each PR slot provides individual interface to peripheral boards. It is configured by each peripheral controller for board-specific connection. 4) The existing system is extensible. The partial reconfiguration mechanism provided in this project supports at least two PR slots. On higher capacity FPGAs, the number of PR slots could be increased. In our existing system, the time used for the dynamic partial reconfiguration process, including the hardware bitstream loading and the software driver loading, is in the order of 10-20ms, which is an insignificant fraction of the Linux boot time.

This work reviews the development frameworks available for the Altera System-On-Chip solutions. These solutions are then compared to solutions available on the Xilinx platform. The RSoC Framework is then presented as an advantageous alternative for the vendor's solutions. This framework is currently available for the Xilinx Zynq platform. Furthermore the work assess the key differences between Xilinx Zynq and Altera Cyclone V SoC platforms and proposes the solution to port the framework to Altera platform. The design and implementation of then RSoC Framework port to Altera Cyclone V SoC is then discussed. Finally the work evaluates the performance of the ported system on the new platform.

L'objectif de cette thèse est de concevoir, d'évaluer les performances énergétiques et d'étudier le comportement en régime transitoire pendant les opérations de chauffage et de démarrage d'un procédé réversible Power To Gas qui est une solution pour l'intégration des énergies renouvelables dans le mix énergétique. L'évaluation des performances énergétiques montre que 66,7% de l'énergie électrique entrante est stockée sous forme de substitut du gaz naturel et que les pertes concernent principalement les étapes de conversion en particulier la conversion AC/DC, la co-électrolyse et la méthanation. Le déstockage de l'électricité (Gas To Power) est réalisé en inversant le RSOC en mode SOFC alimenté par le gaz de synthèse (H2 et CO) produit dans un tri-reformeur. Ce procédé est autonome énergétiquement et produit de la chaleur inexploitée qui est à l'origine de sa faible efficacité de 40%. Une étude de la réponse en régime transitoire est conduite en développant des modèles dynamiques du co-électrolyseur réversible, des réacteurs et des échangeurs par le biais de deux logiciels: Matlab et Dymola. Les résultats permettent de préciser la pénalité énergétique et de revoir l'architecture du procédé prédéfinie en régime stationnaire. Plusieurs stratégies ont été étudiées afin d'optimiser le temps de démarrage et l'énergie consommée. Il s'est avéré que le RSOC est le composant qui consomme le plus d'énergie (71% de l'énergie totale) et qui nécessite le plus de temps de démarrage (60% du temps total) à cause de la quantité du gaz utilisée pour le chauffage et du temps important qu'il faut respecter afin d'assurer une augmentation en température progressive qui évite la détérioration des cellules. / The objective of this thesis is to design, evaluate the energetic performance and study the transient behavior during heating and startup operations of a reversible process Power To Gas process which is a solution for the integration of renewable electricity in the energy mix. Steady state models are first established in Aspen plus. Assessment of energetic performance shows that 66.7% of the electrical energy is stored as a Synthetic Natural Gas and the losses are caused mainly by the converting steps: the AC/DC, co-electrolysis and methanation conversions. Electricity production (Gas to Power) is performed by reversing the RSOC in SOFC mode fueled by synthesis gas (CO and H2) produced in a tri-reformer. This process is energetically autonomous and produces untapped heat which causes its 40% low efficiency. A study of the transient response during heat-up and start-up operations is conducted through the development of dynamic models of reversible co- electrolyzer, reactors and heat exchangers by using Matlab and Dymola softwares. The results allow to specify the energetic penalty and to review the architecture of predefined process in steady state. Several strategies have been studied to optimize the time and the energy consumption. It turned out that the RSOC is the slowest component (60% of total time) with the most energetic consumption (71% of total energy) because of the amount of gas used in heat-up operation and the significant time that must be respected in order to ensure an increase in temperature that prevents the cells deterioration.