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THE METHODOLOGY AND IMPLEMENTATION OF RELAXATION METHOD TO INVESTIGATE ELECTRO-THERMAL INTERACTIONS IN SOLID-STATE INTEGRATED CIRCUITSSo, Biu, 1959- January 1987 (has links)
No description available.
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Development of the capability of testing the accuracy of thermal CAD software for electronic circuit designMacQuarrie, Stephen W. January 1987 (has links)
The capability of measuring surface temperatures of hybrid circuits at the Virginia Tech Hybrid Microelectronics Laboratory has been established. This capability provides a quantitative method for effectively evaluating thermal design software.
Surface operating temperatures were measured and predicted for an operating hybrid circuit. The temperatures were measured using an infrared thermal imaging system, which measures surface temperatures by detecting the infrared radiation emitted and reflected. The accuracy of the measurements has been quantified for variations in surface emissivity, convective cooling condition, and operating temperature range.
The most accurate temperature measurement of a one-resistor circuit was compared to the operating temperature predicted by a lumped-parameter one-dimensional heat transfer analysis. The comparison agreed within the expected limits for this simple analysis and identified areas for possible improvement both of the model and the experimental technique.
Thermal design of a circuit is critical because excessive temperatures are a common cause of circuit failure. Circuit designers rely on computer programs to predict circuit component temperatures because of the high cost of prototype experimentation. Accurate thermal design software that is currently available is too complicated for occasional use by circuit designers. Simple, yet accurate, thermal design software is essential for this type of design, so that circuit layouts can be quickly and easily optimized. / M.S.
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3D high density memory based on emering resistive technologies : circuit and architecture design / Mémoires 3D haute densité à base de technologies résistives : architecture et circuitLevisse, Alexandre 06 December 2017 (has links)
Alors que les mémoires non-volatiles conventionnelles, telles que les mémoires flash à grille flottante, deviennent de plus en plus complexes à intégrer et souffrent de performances et d’une fiabilité de plus en plus réduite, les mémoires à variation de résistance (RRAM) telles que les OxRAM, CBRAM, MRAM ou PCM sont vues dans la communauté scientifique comme une alternative crédible. Cependant, les architectures de RRAM standard (telles que la 1Transistor-1RRAM) ne sont pas compétitives avec les mémoires flash sur le terrain de la densité. Ainsi, cette thèse se propose d’explorer le potentiel des architectures RRAM sans transistor que sont l’architecture Crosspoint et l’architecture VRRAM.Dans un premier temps, le positionnement des architectures Crosspoint et VRRAM dans la hiérarchie mémoire est étudié. De nouvelles problématiques, telles que les courant de sneakpath, la chute de tension dans les métaux ou la surface des circuits périphériques sont identifiées et modélisées. Dans un second temps, des solutions circuit répondant aux problématiques évoquées précédemment sont proposées. Finalement, cette thèse se propose d’explorer les opportunités ouvertes par l’utilisation de transistors innovants pour améliorer la densité ou les performances des architectures mémoires utilisant des RRAM. / While conventional non-volatiles memories, such as floating gate Flash memories, are becoming more and more difficult and costly to integrate and suffer of reduced performances and reliability, emerging resistive switching memories (RRAM), such as OxRAM, CBRAM, MRAM or PCM, are seen in the scientific community as a good way for tomorrow’s high-density memories. However, standard RRAM architectures (such as 1 Transistor-1 RRAM) are not competitive with flash technology in terms of density. Thereby, this thesis proposes to explore the opportunities opened by transistor-less RRAM architectures: Crosspoint and Vertical RRAM (VRRAM) architectures.First, the positioning of Crosspoint and VRRAM architectures in the memory hierarchy is studied. New constraints such as the sneakpath currents, the voltage drop through the metal lines or the periphery area overhead are identified and modeled. In a second time, circuit solutions answering to previously mentioned effects are proposed. Finally, this thesis proposes to explore new opportunities opened by the use of innovative transistors to improve the density or the performances of RRAM-based memory architectures.
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