The main contribution of this dissertation is the demonstration of the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, thus reducing delay, power consumption, and area. To adapt planar microarchitectures to 3D-integrated designs, we study several building blocks that together comprise a substantial portion of a processor s total transistor count. In particular, we focus our attention on three basic circuit classes: static random access memory (SRAM) circuits, associative/CAM logic circuits, and data processing in conventional high-performance processors. We propose 2-die-stacked and 4-die-stacked 3D-integrated circuits to deal with the constraints of the conventional planar technology. We propose high-performance 3D-integrated microprocessors and evaluate the impact on performance, power, and temperature. We demonstrate two different approaches to improve performance: clock speed (3D-integrated processors with identical microarchitectural configurations as the corresponding planar processor run at a higher clock frequency), and IPC (3D-integrated processors accommodate larger-sized modules than the planar processors for the same frequency). We demonstrate the simultaneous benefits of the 3D-integration and highlight the power density and thermal issues related to the 3D-integration technology. Next, we propose microarchitectural techniques based on significance partitioning and data-width locality to effectively address the challenges of power density and temperature. We demonstrate that our microarchitecture-level techniques can effectively control the power density issues in the 3D-integrated processors. The 3D-integrated processors provide a significant performance benefit over the planar processors while simultaneously reducing the total power. The simultaneous benefits in multiple objectives make 3D-integration a highly desirable technology for use in building future microprocessors. One of the key contributions of this dissertation is the temperature analysis that shows that the worst-case temperatures on the 3D-integrated processors can be effectively controlled using microarchitecture level techniques. The 3D-integration technology may extend the applicability of Moore s law for a few more technology generations.

Thesis (M.S.)--Mississippi State University. Department of Computer Science. / Title from title screen. Includes bibliographical references.

Thesis (M. Phil.)--University of Hong Kong, 1999. / Includes bibliographical references (leaves 71-75).

Thesis (MSc. (Hons.))--University of Western Sydney, 2004. / A thesis presented to the University of Western Sydney, College of Science, Technology and Environment, School of Science, Food and Horticulture, in fulfilment of the requirements for the degree of Master of Science (Honours). Includes bibliographies.

The primary aim of this study was to determine the relationship between the practice of transformational leadership and a high-performance culture.The study hypothesized a positive relationship between transformational leadership and a high-performance culture. It also examined the predictive value of transformational leadership behaviours to the different dimensions of a high-performance culture. The survey included a sample of 209 leaders fromvarious South African organisations. The Multifactor Leadership Questionnaire (MLQ5X Form 5X) was completed by these leaders and their subordinates. The High-performance Culture Questionnaire was completed by the subordinates only. Findings indicated positive correlations between transformational leadership and a highperformance culture. Furthermore, differences were found to exist in the predictive value of transformational leadership behaviours to the various dimensions of a high-performance culture. The theoretical and practical implications of these findings were discussed. / Dissertation (MCom)--University of Pretoria, 2016. / tm2016 / Human Resource Management / MCom / Unrestricted

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<p dir="ltr">Graph-structure data is prevalent because of its ability to capture relations between real-world entities. However, graph data analyzing applications, including traditional and machine-learning-based approaches, are highly resource-demanding, necessitating massively parallel hardware like distributed clusters. Domain-specific systems, which aims to hide the hardware complexity from application users, suffers from the communication and computation efficiency problems.</p><p dir="ltr">This thesis tackles the problems with a set of novel specialized system designs for each category of workloads. For graph analytics workloads, we propose to enforce precise loop-carried dependency propagation to reduce redundant communication and computation in our SympleGraph system. SympleGraph achieves up to 2.30x and 7.76x speedups over Gemini and D-Galios, two state-of-the-art systems. For graph pattern mining workloads, we propose to co-design the pattern decomposition algorithm and compilation techniques to improve computation efficiency, and leverage application-characteristics-aware optimizations to reduce and hide communication overhead efficiently in our DecoMine and Khuzdul systems, respectively. Our extensive experiments show that, DecoMine and Khuzdul significantly outperform previous state-of-the-art solutions. For graph neural network training, we propose to introduce pipelined model parallelism for deep model training to reduce the worst-case communication complexity by a factor of model depth. With the proposed technique, our system, GNNPipe, can reduce the communication volume by up to 22.89x and speed up the training by up to 2.45x.</p>

<p>High performance fighter aircraft such as the F-16 experience aeroelastic Limit Cycle Oscillations (LCO) when they carry certain combinations of under-wing stores. This `store-induced LCO' causes serious problems including airframe fatigue, pilot discomfort and loss of operational effectiveness. The usual response has been to restrict the stores carriage envelope based on flight test experience, and accept the accompanying reduction in mission performance.</p><p>Although several nonlinear mechanisms - structural as well as aerodynamic, have been proposed to explain the LCO phenomenon, their roles are not well understood. Consequently, existing models are unable to predict accurately AND reliably the most critical LCO properties, namely onset speed and response level. On the other hand, the more accurate Computational Fluid Dynamics (CFD) based time marching methodology yields results at much greater expense and time. Clearly, there is a critical need to establish methods that are more rapid while providing accurate predictions more in line with flight test results than at present. Such a capability will also aid in future aircraft design and usage.</p><p>This work was undertaken to develop a better understanding of nonlinear aeroelastic phenomena, and their relation to classical flutter and divergence, with a particular focus on store-induced LCO in high performance fighter aircraft. The following systems were studied: (1) a `simple' wing with a flexible and nonlinear root attachment, (2) a `generic' wing with a flexible and nonlinear wing-store attachment and (3) the F-16 aircraft, again with nonlinear wing-store attachments.</p><p>While structural nonlinearity was present in all cases, steady flow aerodynamic nonlinearity was also included in the F-16 case by the use of a Computational Fluid Dynamics model based on the Reynolds Averaged Navier Stokes (RANS) equations. However, dynamic linearization of the CFD model was done for the present computations. The computationally efficient Harmonic Balance (HB) nonlinear solution technique was a key component of this work, with time marching simulations and closed form solutions being used selectively to confirm the findings of the HB solutions. The simple wing and the generic wing were both modeled as linear beam-rods whose displacements were represented using the primitive modes method. The wing aerodynamic model was linear (quasi-steady for the simple wing and based on the Vortex Lattice Method for the generic wing), and the store aerodynamics were omitted.</p><p>The presence of a cubic restoring force (of hardening or softening type, in stiffness or in damping) at the root of the simple wing led to several interesting results and insights. Next, various nonlinear mechanisms including cubic restoring force, freeplay and friction were introduced at the wing-store attachment of the generic wing and these led to a still greater variety in behavior. General relationships were established between the type of nonlinearity and the nature of the resulting response, and they proved very useful for tailoring the F-16 study and interpreting its results.</p><p>The Air Force Seek Eagle Office/Air Force Research Laboratory provided a modal structural model of an LCO-prone store configuration of the F-16 aircraft with stores included. In order to investigate a range of stores attachment configurations, the analysis required modification of the stiffness and damping of the wing-store attachment. Since the Finite Element model of the wing and store structure was not available, the modification was achieved by subtracting the store and adding it back with the necessary changes to the store or attachment using a dynamic decoupling/coupling technique. The modified models were subjected to flutter/LCO analysis using the Duke Harmonic Balance CFD RANS solver, and the resulting flutter boundaries were used in combination with the HB method to derive LCO responses due to the wing-store attachment nonlinearity.</p><p>Comparisons were made between the simulation results and the F-16 flight test LCO data. While multiple sources of nonlinearity are probably responsible for the wide range of observed LCO behavior, it was concluded that cubic softening stiffness and positive cubic damping were the more likely structural mechanisms causing LCO, in addition to nonlinear aerodynamics.</p> / Dissertation

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / The wide use of standard packet telemetry protocols based on the Consultative Committee for Space Data Systems (CCSDS) recommendations in future space science missions has created a large demand for low-cost ground CCSDS processing systems. Some of the National Aeronautics and Space Administration (NASA) missions using CCSDS telemetry include Small Explorer, Earth Observing System (EOS), Space Station, and Advanced Composite Explorer. For each mission, ground telemetry systems are typically used in a variety of applications including spacecraft development facilities, mission control centers, science data processing sites, tracking stations, launch support equipment, and compatibility test systems. The future deployment of EOS spacecraft allowing direct broadcast of data to science users will further increase demand for such systems. For the last ten years, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center (GSFC) has been applying state-of-the-art commercial Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) technology to further reduce the cost of ground telemetry data systems. As a continuation of this effort, a new desktop CCSDS processing system is being prototyped that offers up to 150 Mbps performance at a replication cost of less than $20K. This system acts as a gateway that captures and processes CCSDS telemetry streams and delivers them to users over standard commercial network interfaces. This paper describes the development of this prototype system based on the Peripheral Component Interconnect (PCI) bus and 0.6 micron complementary metal oxide semiconductor (CMOS) ASIC technology. The system performs frame synchronization, bit transition density decoding, cyclic redundancy code (CRC) error checking, Reed-Solomon decoding, virtual channel sorting/filtering, packet extraction, and quality annotation and accounting at data rates up to and beyond 150 Mbps.