Thesis (M. A.)--University of Hong Kong, 2005. / Title proper from title frame. Also available in printed format.

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Most high speed vessels are fitted with powerful high speed engines which are installed in confined spacesa nd, as a consequencec, ausea n extremely high level of noise and vibration. Often structure-borne sound power is transmitted to a sound carrying structure from a source via a number of contact points. In turn, the noise and vibration are propagated in the structure and could possibly cause an undesired noise radiation. In this study, a model for predicting power flow based on the mobility theory has been addressed. The unique parts of the study include the establishment of the relationship of mobility functions with respect to four-pole parameters and the dynamic stiffness coefficients of a coupled machine/mount/foundation system. Also expressions to represent the sound input power, the output power and the transmitted power in relation to mobility functions are clarified. From a detailed analysis of relevant literature, it is shown that no validated models for predicting the propagation of structure-bome noise within the intermediate frequency range of 125 Hz to lkHz exist. As a consequence, a new numerical stress wave model has been developed to bridge this knowledge gap. This innovative approach extends the earlier works of Cremer, Heckl and Ungar in the field of stress wave propagation. Finally, a novel holistic model has been developed to line up the transmission, propagation and radiation predictions of a machine induced noise and vibration in ship's structure to take in account the fluid-structure interaction effect. A number of experiment measurements have been performed to validate the established models. From the comparisons, the prediction models are shown to be credible with an accuracy higher than 95 per cent. The established models are of a generic nature and can be applicable to diverse engineering fields regarding to the predictions of structure-borne noise and vibration transmission, propagation and radiation. Applications of these models to characterize the vibration reduction countermeasures,a s in the case of resilient mounts and squeeze-film damping plates, from a machine are also discussed.

Data transfer rates on printed circuit boards are quickly approaching speeds that challenge the limits of todays technology. Inter-chip communication has increased dramatically. Currently data rates have reached 3.125 Gb/s on standard circuit board, but chip-to-chip digital communication has currently reached a plateau and several problems need to be addressed to significantly increase data transfer rates. Inductive and capacitive components of far end crosstalk (FEXT) conveniently cancel each other as they propagate on an interconnect transmission line, however the inductive and capacitive components of near end crosstalk(NEXT) add together and interfere with signals on adjacent receivers.<p>This paper proposes a novel solution for canceling crosstalk by adding extra circuitry to the receiver within the integrated circuit. This digital circuit delivers one of three appropriate levels of crosstalk compensation to the incoming signal. Since the circuit is digital, simple blocks can be used to implement it on a complimentary metal-oxide semiconductor (CMOS) integrated circuit and consume very little extra silicon.<p>This paper presents the compensation circuit and reports the results of the simulations, which demonstrate improved performance over the standard system. The compensation circuit is specifically aimed at adjacent input and output lines on a microchip. Simulations of a typical circuit board configuration operation have shown crosstalk that is only 15 dB lower than a received attenuated signal. The crosstalk cancellation circuit has been shown to improve this by as much as 10 dB.

Data transfer rates on printed circuit boards are quickly approaching speeds that challenge the limits of todays technology. Inter-chip communication has increased dramatically. Currently data rates have reached 3.125 Gb/s on standard circuit board, but chip-to-chip digital communication has currently reached a plateau and several problems need to be addressed to significantly increase data transfer rates. Inductive and capacitive components of far end crosstalk (FEXT) conveniently cancel each other as they propagate on an interconnect transmission line, however the inductive and capacitive components of near end crosstalk(NEXT) add together and interfere with signals on adjacent receivers.<p>This paper proposes a novel solution for canceling crosstalk by adding extra circuitry to the receiver within the integrated circuit. This digital circuit delivers one of three appropriate levels of crosstalk compensation to the incoming signal. Since the circuit is digital, simple blocks can be used to implement it on a complimentary metal-oxide semiconductor (CMOS) integrated circuit and consume very little extra silicon.<p>This paper presents the compensation circuit and reports the results of the simulations, which demonstrate improved performance over the standard system. The compensation circuit is specifically aimed at adjacent input and output lines on a microchip. Simulations of a typical circuit board configuration operation have shown crosstalk that is only 15 dB lower than a received attenuated signal. The crosstalk cancellation circuit has been shown to improve this by as much as 10 dB.

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Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 57-59). Also available via the Internet.

This work investigated the design of classical and optimal control strategies to actively control the flexible modes of a high speed railway vehicle body. It explored the novel idea of adding a third actuator at the centre of the vehicle body to suppress the flexible body modes (i.e. first symmetrical and first asymmetrical) in addition to the actuators located across the front and rear secondary suspensions. The aim is to minimise the level of vibration and improve the ride quality (comfort). Both the two and three actuators are considered in the classical and optimal control strategies investigated.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / In order to meet the high-speed and high-density recording requirements for today's development and testing environments, we are seeking to merge the cutting edge technologies of tiny, high-performance disk drives and field programmable gate arrays (FPGAs) to build a high-speed compact disk recorder (CHSDR). Specifically, we designed, built, and tested a multi-drive controller that handles the interleaving of data to eight inexpensive IDE drives. These drives and controller comprise a "cell" capable of transferring data at 2.45 MB/sec (4 to 5 times the rate of a single drive). Furthermore, these "cells" can be run in parallel (with a single controller interleaving data between the cells). This "tree" effect multiplies the data rate by the number of cells employed. For example, 8 cells (of 8 drives each) can reach nearly 20 MB/second (sustained) and can be built for less than $30,000. The drives we used are the size of match boxes (the Hewlett Packard KittyHawk). These tiny drives hold 42 megabytes each and can withstand 150 Gs while operating. The cell controller is a Xilinx 4005 FPGA. Furthermore, we've designed a 120 MB/sec RAM FIFO to buffer data entering the system (to account for unavoidable drive seek latencies). In short, the compact high-speed disk array is a small, relatively low cost recording solution for anyone requiring high data speed but modest data volume. Missile shots, nuclear tests, and other short-term experiments are good examples of such requirements.